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Unformatted text preview: Texas State University
The Ingram School of Engineering
Electrical Engineering Program EE 4352: Introduction to VLSI Design Name: W Test 1 Spring 2011  02(24t2011]11:00 am — 12:20 am] Please Read the following instructions before you start.
Good Luck 1. This is a closedbook closednotes test. 2. Equations are provided. 3. Solve all of the following m problems in any order you wish. 4. Start solving the problems in the space allocated and use more paper sheets as
needed. 5. Number your answer sheets properly. Dr. Hassan Salamy Page 1 Problem 1 3) Brieﬂy answer the following questions.
1. What does CMOS stand for?
2. What is self loading?
3. What does NRE cost stand for? Give three examples.
4. Name three classes of parasitic in wires. b) Given a ring oscillator of 9 inverters. Assume for each inverter tpm = 62.43ps and tpLH =
58.23ps 1 Draw the ring oscillator circuit.
2— Find tp for one inverter.
3 Find tp for the ring oscillator.
\ 4 Find the Find the frequency of the oscillation.
5— Find PDP for the ring oscillator assuming the power dissipation of one inverter is 30 pW. c) Consider the ﬁgure below for the body effect on an NMOS device.
1— Explain the effect of the well bias on the threshold voltage.
2 What happens when V53 becomes smaller than —0.6 V in an NMOS.
3 Using the graph below, ﬁnd meor V35 = —1 V. Given (DF : 0.3V and bodyeffect
coefficient = 0.4. S
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different V65 values, respectively. o 0.5 1 1.5 2 2.5
Vos (V) 03‘)“ a pa) Label the source, drain and gate terminals on the inverter ﬁgure for the PMOs and the
____/~ NMOS. b) Draw the Corresponding IV—plot for a PMOS for the following V55 values: (—1.5 V, 1 V,  0.5 V and 0 V).
c) Using part (a) and any other analysis, find V55", V959, V554,, and Vosp in terms of Vin and
Vout (2) Use the equalities in part (c) and the fact that iosp = 405“, show the step by step
{5&3 transformation of the PMOS lVplot in part (b) to a graph with Vin as the xaxis and IDn as
the yaxis. Assume VDD = 2.5 V. Explain. Dr. Hassan Salamy Dr. Hassan Salamy Page 6 Problem 3 Fill the table below by finding the mode of operation of each of the devices based on the given
characteristics. Explain your answer. Modeofoperatim Emlaaatten. $C\“\J (Cs310w llﬂhf‘tﬁf‘
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V51) L Vi Uﬂl? : _} Dr. Hassan Salamy Page 7 Problem 4 Consider the circuit in the ﬁgure below. W—DO—Di :09. = 1 CL: 125 09.1— a) In order to drive a large capacitance (CL) from a minimum size gate (with input
capacitance C34), you decide to introduce a threestaged buffer as shown in the
ﬁgure above. Assume that the propagation delay of the minimum size inverter is 8
ps. Also assume that the input capacitance of a gate is proportional to its size.
Determine the sizing of the three additional buffer stages that will minimize the propagation delay. Find this minimum propagation delay. b) If you could add any number of stages to achieve the minimum delay, how many
stages would you insert? What is the minimum propagation delay in this case
assuming the propagation delay of the minimum size inverter is 8 ps? c) Find the minimum propagation delay of a chain of 8 inverters assuming the
propagation delay of the minimum size inverter is 8 ps. d} Find the total propagation delay of a chain of 5 inverters such that the gate
capacitance of inverter (1' + 1) is five times that of inverter (1'). Assume that the gate
capacitance of the 5th inverter is 1/5 CL Assume also that the propagation delay of
the minimum size inverter is 8 ps. W
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mm L J 1% LC)“L‘1 T. \‘QI pé {ff/i) Dr. Hassan Salamy Page 9 Problem 5 A Answer the foilowing three questions: 1 An NMOS has a drawn L of 1.4 pm and a drawn Wof 2.6 pm. During processing,
active region is expanded all around by 0.12 pm and Polysilicon is shrunk all
around by 0.19 pm. a) Calculate L of the transistor that contributes to the current.
b) Calculate W of the transistor that contributes to the current.
2 What is Nselect?
3 Find A for a technology of 0.4 pm. 3— In this problem, the circuit is implemented in 0.25um technology, and all the transistors
have the minimum channel lengths.
Consider the CMOS inverter in the Figure (a) below. If the NMOS transistor has channel
width, Wn, and the PMOS transistor has channel width, Wp, label the voltage transfer
characteristics from Figure (b) that correspond to following device sizes:
A: Wn = 5pm, Wp = 5pm w“
B: Wn= 1pm, Wp= 5pm ‘73? 1 l
C: Wn = 5pm, Wp = 1pm
Briefly explain your answers. VDD
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