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EE 4352 - Exam 1 - Spring 2011

EE 4352 - Exam 1 - Spring 2011 - Texas State University The...

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Unformatted text preview: Texas State University The Ingram School of Engineering Electrical Engineering Program EE 4352: Introduction to VLSI Design Name: W Test 1 Spring 2011 - 02(24t2011]11:00 am — 12:20 am] Please Read the following instructions before you start. Good Luck 1. This is a closed-book closed-notes test. 2. Equations are provided. 3. Solve all of the following m problems in any order you wish. 4. Start solving the problems in the space allocated and use more paper sheets as needed. 5. Number your answer sheets properly. Dr. Hassan Salamy Page 1 Problem 1 3) Briefly answer the following questions. 1. What does CMOS stand for? 2. What is self loading? 3. What does NRE cost stand for? Give three examples. 4. Name three classes of parasitic in wires. b) Given a ring oscillator of 9 inverters. Assume for each inverter tpm = 62.43ps and tpLH = 58.23ps 1- Draw the ring oscillator circuit. 2— Find tp for one inverter. 3- Find tp for the ring oscillator. \ 4- Find the Find the frequency of the oscillation. 5— Find PDP for the ring oscillator assuming the power dissipation of one inverter is 30 pW. c) Consider the figure below for the body effect on an NMOS device. 1— Explain the effect of the well bias on the threshold voltage. 2- What happens when V53 becomes smaller than —0.6 V in an NMOS. 3- Using the graph below, find meor V35 = —1 V. Given (DF : 0.3V and body-effect coefficient = 0.4. S 0.9 (n H ‘3 I185 0.3 D 9.75 - . 415 o VBS (V) ——WW Page 2 Dr. Hassan Salamy CKxAC '3{N\CGMRA\BC‘\CT , T n ‘_ ‘ 7 '3 \b x I H; chr‘ \A' ‘ p‘vak 39kt {VN\“V\51L CD‘QQCAh/Lmtf al‘Q—‘ix \3 1 ”IA. ‘ _ .. .- , m _ , —r;l (\cmwani 3H“, (KldUJ‘tfi‘L, \Uu (5 "\ M49: vf www-U‘ awt game-0%, ’1 w.“ mum-rm avenues-w fic‘s x (‘F’DUZSm awé "Lyme pU‘m& a man \< Rene—\ft‘kxxfifl o 66:55? :34 Vfi/WPW‘CW“ L‘) '25 §Crmn cX Pam’nim‘v wx “We“? a (Nemfiskme e ivxé‘w‘H—MQC o {q QuCAVR/fl CD by “MEX @3C{\1¢p\o( Ojr (K \uuukcd , . ‘3 mm . -_ i - 1‘ s[ -. fro # #1, MM 2 61,10,255, MHZ oj‘P‘DP 5 .___. 7Q: - . _ ‘ ._.?‘\ _ _ ‘ no? a v ,Lp ; w 'K'EO.‘AW\UC4.,m-a5 1:75;“? Effist Dr. Hassan Salam Pa e3 y :D g ‘ > We U \fst‘fihs c Vk_ *\/\y'c;~. \XC‘N é [wkgw qgo Chan-51.x W53 . "J-FVV {"virthkl. ‘-Jo[{h}f 1A\‘?[. (11.2?th flunkd/J Milt/“(7 ”H.371 ”VJ-11 CL [a m“ [DC‘AVI In 6;“th “(gr ‘7L{L{ (4,ng 7/0 ‘/U'-1L7f'0‘v‘ [OFC’er-‘t lg r “'1 1+ [5) ”C“; [31901 It +41: Tc. {“3 11c; { fit-tcuq M L/of/L7C #0 [3L 3k (iv-v} (\trr‘fb/IC a} Um g -C..(;\/ ‘f’lu 717i: 5kg M uc; [1&7 -( 1/ lat ) {LL/'81) [(4 étv or Dr. Hassan Salamy Page 4 AMA Problem 2 The figures below show the circuit diagram of a CMOS inverter and the lV—plot of an NMOS for different V65 values, respectively. o 0.5 1 1.5 2 2.5 Vos (V) 03‘)“ a pa) Label the source, drain and gate terminals on the inverter figure for the PMOs and the ____/~ NMOS. b) Draw the Corresponding IV—plot for a PMOS for the following V55 values: (—1.5 V, -1 V, - 0.5 V and 0 V). c) Using part (a) and any other analysis, find V55", V959, V554,, and Vosp in terms of Vin and Vout- (2) Use the equalities in part (c) and the fact that iosp = 405“, show the step by step {5&3- transformation of the PMOS lV-plot in part (b) to a graph with Vin as the x-axis and IDn as the y-axis. Assume VDD = 2.5 V. Explain. Dr. Hassan Salamy Dr. Hassan Salamy Page 6 Problem 3 Fill the table below by finding the mode of operation of each of the devices based on the given characteristics. Explain your answer. Modeofoperatim Emlaaatten. $C\“\J (Cs-310w llflhf‘tfif‘ [/1 Vt”- Mk ‘1 LT i7 qujvk \‘ll20\ Cigar—7 via 5:: V13 — U?‘ V10 UL - 0 ll i-i/ G7 Uh-L-L —. Ii JZT> ( L {L V a) ‘7: l 1.5 V43 ; \fWSWUE (Erica'— 5'} Jfib‘v‘l‘ " 27 V51) L Vi Ufll? : _} Dr. Hassan Salamy Page 7 Problem 4 Consider the circuit in the figure below. W—DO—Di :09. = 1 CL: 125 09.1— a) In order to drive a large capacitance (CL) from a minimum size gate (with input capacitance C34), you decide to introduce a three-staged buffer as shown in the figure above. Assume that the propagation delay of the minimum size inverter is 8 ps. Also assume that the input capacitance of a gate is proportional to its size. Determine the sizing of the three additional buffer stages that will minimize the propagation delay. Find this minimum propagation delay. b) If you could add any number of stages to achieve the minimum delay, how many stages would you insert? What is the minimum propagation delay in this case assuming the propagation delay of the minimum size inverter is 8 ps? c) Find the minimum propagation delay of a chain of 8 inverters assuming the propagation delay of the minimum size inverter is 8 ps. d} Find the total propagation delay of a chain of 5 inverters such that the gate capacitance of inverter (1' + 1) is five times that of inverter (1'). Assume that the gate capacitance of the 5th inverter is 1/5 CL Assume also that the propagation delay of the minimum size inverter is 8 ps. W Dr. Hassan Salamy Page 8 - m“. 9'1 (9 gas-“ma Pf: C) q )1: fi M: 1.1L“ , \“ mfl a. “QR a: 1:2 \vx(C\ \ , / L J‘ - “:5 ‘2}101L: Lu \\ LA] J ' «63" N u) g ‘ I W >5 <’ yxjyj'flIXk. If. Zr) ‘ N 14m [” if) \\ U 4% :QS}LE§¢3)L\+1QupW \/ ‘7’ ?/L{.)'_ [[33 I ‘ —— 1 A a, 1 (EC :- 5 i K J @l “-9: I if” 893 O :5 : i—Czs— Ajax/AZ Z// Nflfi ] g ”$qu $;11'§' ., 321 (‘1 3 7'5 :éflffgffifi 5; 7 . (J. L1 .5 y"! a, W“ 52,540+ (14“ 9: F3. .m -, L818. éz " :6 *‘f ’ . Cl - LL M . f . i 1* ”4“ 530*“ gflxfihfifl UTE-3:) {p ' 1/413 {/i 1.) f rfl‘§_f_-"- “ 5' (bkflflUH-GE’E 346115;}? :35 {K‘Khfli(MSM'LH‘SYLLHSYA , . % C5 . mm L J 1% LC)“L‘1 T. \‘QI pé {ff/i) Dr. Hassan Salamy Page 9 Problem 5 A- Answer the foilowing three questions: 1- An NMOS has a drawn L of 1.4 pm and a drawn Wof 2.6 pm. During processing, active region is expanded all around by 0.12 pm and Polysilicon is shrunk all around by 0.19 pm. a) Calculate L of the transistor that contributes to the current. b) Calculate W of the transistor that contributes to the current. 2- What is N-select? 3- Find A for a technology of 0.4 pm. 3— In this problem, the circuit is implemented in 0.25um technology, and all the transistors have the minimum channel lengths. Consider the CMOS inverter in the Figure (a) below. If the NMOS transistor has channel width, Wn, and the PMOS transistor has channel width, Wp, label the voltage transfer characteristics from Figure (b) that correspond to following device sizes: A: Wn = 5pm, Wp = 5pm w“ B: Wn= 1pm, Wp= 5pm ‘73? 1 l C: Wn = 5pm, Wp = 1pm Briefly explain your answers. VDD Vin | VM (8) G) 1);.Q 3mm 55; +\(U-_._.\ Ark/— TQL‘gL c; thatch 0} \Ir omit“ respect L“ 1“!"an {-5 large £6: Ui‘f‘l‘ufin L -\ .huir (“a fiwmllr—Y 'ptC-V welbui‘l _ ‘ - .. , . l/‘V - “€(Lku‘3 (5 .5, +M {lg—yw\\:\t't)l\\\'\'f—1 th-Q‘fflflCLM-C'V‘} {LU-\- V L04, \U\[\L'CL.3| we) P/ww .- ‘f‘ltwc [-3 iii-Ht. ((9.)qu -!ju~1' NCLVCJVL-l ‘V’ofmk “ain‘t , 5:0 \_‘ \b Dr. Hassan Salamy Page 10 *c CAM—<3." ' .,.\]'3(\r.c\- {b ugs‘Ym-{e “a"; 4(ch Rog: 5.0;“, rived“ \'.V\. 'A’kg LiDIT chbfiam @ gar/[flung (CC! k1 1| "Shiv-113)») ' I] W Dr. Hassan Salamy Page 11 ...
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