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EE_4352_Exam2_Spring_2011

EE_4352_Exam2_Spring_2011 - Texas State University The...

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Unformatted text preview: Texas State University The Ingram School of Engineering Electrical Engineering Program EE 4352: Introduction to VLSI Design Name: C r :1: {am Test2 Spring 2011 - 04(12Z2011111:00 am — 12:20 pml Please Read the following instructions before you start. L . 00 'm: . This is a closed-book closed-notes test. m Equations are provided. Solve all of the following m problems in any order you wish. Start solving the problems in the space allocated and use more paper sheets as needed. 5. Number your answer sheets properly. P9P“ Dr. Hassan Salamy Problem 1 Briefly answer the following: a) What is the difference between a latch and a flip flop? b) We know that an odd number of inverters in a closed loop can be used as a ring oscillator. Generally speaking, what can an even number of inverters in a closed loop be used for? c) What is the difference between combinational and sequential logic? d) Draw the transistor—based circuit using static CMOS of a NAND3 and a NOR3 gates. If you have the choice of using either in a certain design, is it better to use a NAND gate or "'a NOR gate and why? 8) How many transistors do you need to design an n-input NAND gate using: (i) static CMOS, (ii) Pseudo NMOS, and (iii) Dynamic CMOS? f) Draw a NORZ using dynamic CMOS. @ Lalo?» - I/tuzf Semsi'ji‘ud Ci‘ré‘uw’i $1144 [Gassefi i"“[00{5 J6 Q when flu: c/ock 1‘5 Ava/34 /or kw) .. lira”; arew-l Moalc info-i Sawcftd oi»- 4L6. fall/[V7 edlclt ‘ 5‘: LC clock [5 lusts: fir-la [c 05kg,“ ch01":- vs [09.) av luavx Flirlllvp - 637$ ficwsr‘Jc-oe ci'rcw'ilS “Ma“; Sam/7M; JIM: "raft/1’) am 6‘ FAX}; JVMWSDQIUH . burial 05w? laid/cf) (:9 All 70;; CLELVVK aux. euczm Mom bar of i"V‘~UC'r‘ler$; flémrc will 19"» Md afiflt‘llfi-‘lifl‘v‘; 77w: [morale-rs mill d-lglail-r‘:e aka lmoicl “l’lmeir What fl” (”am At 0366‘ as at buff“ . lfi/ )l/Lc ”Wuhan/wk prc’rwlgf CE :-—- lZ—l 71C fliflf‘y} _ (ii/11; ir'fi’kf f 5'6 JiUC C V‘.CO.E-1<_éi’ “GP/i‘émaj QM, A Se (quewrfuq AWL '3f'i’C‘l’i‘Ifi 1‘75‘ '7Llit‘i5l 5-60me-r/rai Cr'rcmffi eemPolc flfvv— ou‘lPu‘l [”662 all“ at“ (“Full <1,ch “5'1le 3 4nd “illrmvlfilcvlfl I‘S U‘PthL-lfé louseé am 0k. clack, ”dimlli‘fla‘lig 54¢] (ir'rauf‘ils f‘JMP[CIi\/L£AF~+ 736C) {61“ *llbvcthk‘)‘; So ‘M‘C‘j Cerf *(EJRC‘liOirLB an ['1 53-]: J’iiérrr l‘filflvli GLVLJ‘ my: éajcé mt fl/ockfik Page 2 Dr. Hassan Salamy -"71e/ flané’3 Luca/J I56 7L1: Afg‘ffi/ 5! 7U” 7490—5171“: 7%6 JUA'AJBB 1555.5 3 i'flpu’wis ("A PMUfi fin [Dmffaiféfgy'fu‘fi Akrs Up [333 float: Dr. Hassan Salamy I Page Problem 2 a) Draw a static CMOS circuit for the following logic function Y = X1X2 + X1X3 + X; using the minimum number of transistors. Size the devices so that the output resistance is the same as that of an inverter with an NMOS W/L = 2 and PMOS W/L = 4. b) Draw a static CMOS circuit for the following logic function Y = X1 6—) X2 using the .1 minimum number of transistors. [UoSr immature 5tCJv-J c) Draw the stick diagram of a 3*input NOR gate. Show all your steps. Cfiuc} Y7- X‘Xz‘? XIIX34XL‘ ’ we was i m Dr. Hassan Salamy Dr. Hassan Salamy I Page 5 Problem 3 Consider the circuit in Figure 1. Given the following values for gate X(p,g); n—input NANDln, (n+2)/3) and n—input NOR(n, {2n+l)/3). 7' a fig: . a” t‘ .— 39.: rem E (93" 1: J OSLEibtfl ‘5 we? .. i—i 3:" = ' .— .9'5 x '3; .r'=1 ’ [J o = tpo (ftp.- ill” W 2/) ~ a) Find the path logical effort 6. ) Find the value of B. c) Find the optimal stage effort h. d) Find the fan out factorfi-for each ofthe gates in the path. ) Find the sizing of each of the gates so that the total delay of the path is minimized. 1‘) Find the minimum delay of the logic circuit. Assume tpo = 20 ps. Figure 1: A logic path ‘1 3 ® G1 : (QL‘YI‘aWCT/a\( EXL7I%\ ._:_ :3; Q Mo brmnflJMucx its: ll © F: mica, '2 lleiaalle 5' ”W h __ n H .2 2."! u = are W ' \ 5 .. 212135030» ~——- “' 9“ Dr. Hassan Salamy Page 6 ’é 5 ’5! @ 5‘ t \ (KLMLSM "" 5‘ " -. 3; as M1 = @” -. Sq 5;} Q. 0.5 _* (@13)L\‘693E0l ’33 “.5 \ Sb : S\ 5: 4:qu ] -.~. (1.903%)(69‘0 m ’03 Q So i I 1 "5'3 \ 511.1 - [L'bfiLx-s‘aWLDA‘OC“ U5 [#3) . " Stgz—g Such 1‘1,” SA 3 o) \3131 \$&:1,‘383 is“; h3g3 Sgt—fl. $.H!\SA —.-.. L3H] {}>1J02(P24$fl\ gsmwwz; qzl “I 1 20%” [(1 Jr‘ (13%)} + L3 + Magma-533 +L1ek,casth * LN L2«3)Cr\\ ~r L’swwwi’l 0 = 4% (ZPHMCW/M I 3015 9-3 Dr. Hassan Salamy Page 7 Problem 4 a) Design a Half—Adder using CMOS—TG and static CMOS gates. b) Design an SR latch using NOR gates only. New replace each NOR gate in your SR latch design with a NAND gate. What is the truth table of your NAND gates only design? Can this design be still used as a latch? Explain. .il Dr. Hassan Salamy ' Page 8 Dr. Hassan Salamy Page 9 Problem 5 3) Why are there discrepancies in the VTC of a 2 input NAND gate shown in the figure below? Explain your answer. VTM. ' “no “i“ ‘Y (495*?- '* UiWi1fl 3 " “95f :Lao due. i—o Curd” b) Find an expression in terms of PA and PB of the transition probability of a 2—input NAND and 2— input NOR. Explain your answer. M c) Find the total switching activity in the circuit below. Assume P(A)= 0.4 PB 2.0 3 and P(=C) 0.2. __ .. Pv- (Vim/ii. WM (SIWJ’. \ffib 6g“ N7, “(:5 Page 10 Dr. Hassan Salamy Vb "_ Ex“) I??? K m a, \— 9033:, “a: E - 1. K9030 \L\' okPfi) 9W .. wx » k193i. an. KNOW“ "1 _ \" 91. ' ' .. [:21 its 6 - {VKVWJLP $\ $.93 % __ fl -9 « (Q ' g ‘ ‘ 3r 3r {-3 6x - {A “:5“ ‘°\ L‘ Q} -QlAU-pvhw .WGCWVEJM- W“ ‘3}? 4%; MW“ avgmb w‘rtfi‘fi 0 swrra’nt ,%L H)“ an 3AM. prohm‘oflavfi Aknwfig “(WW-*5 0% L- M“ \A C Page 11 Dr. Hassan Salamy ...
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