Exam (37).pdf - Question Perform a manual or computer-based logic simulation similar to that given in Figure 1 for the SR latch shown in Figure 2

Exam (37).pdf - Question Perform a manual or computer-based...

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Question: Perform a manual or computer-based logic simulation similar to that given in Figure 1 for the SR latch shown in Figure 2. Construct the input sequence, keeping in mind that changes in state for this type of latch occur in response to 0 rather than 1. Figure 1 Logic Simulation of SR Latch Behavior FIGURE 2 Latch with NAND Gates Answer : Consider the latch Figure 6-6(Refer text book). VHDL Code for construct the input sequence to latch: library ieee;
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use ieee. std_logic_1164.all; entity invert_SR_Latch is PORT( S,R: in std_logic; Q, QBAR: out std_logic); end invert_SR_Latch; Architecture behavioral of invert_SR_Latch is begin P1: PROCESS(S,R) variable x: std_logic; begin If(S='0' and R='1')then x :='1'; elsif(S='0' and R='0')then x :='Z'; elsif(S='1' and R = '0')then x :='0'; elsif(S='1' and R = '1') then x := x; end if; Q <= x; QBAR <= not x; end PROCESS; end behavioral;
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Simulation Code: LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values
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