EE4353_Lecture_5_CMOS-Operation_And_Scaling

EE4353_Lecture_5_CMOS-Operation_And_Scaling - EE 4353...

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EE 4353 Lecture 5 CMOS Operation and Scaling Rules Professor Hsing-Huang Tseng Sep. 12, 2011
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Schematic drawing of an N-channel MOSFET in the off state (a) and the on state (b). (c) and (d) show a P-channel MOSFET in the off and the on states . Off On Vg = 0 Vg = V dd Vg = 0 Vg = V dd Off On
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For CMOS no current flow from V dd directly to the ground For NMOS or PMOS, as the transistor is on there is current flow from V dd to ground Taur/Ning Sec 5.1.1 S S D D
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7 Semiconductor CMOS Transistor NFET and PFET can be fabricated on the same chip
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CMOS (Complementary MOS) Inverter Q: A CMOS inverter is made of a PFET pull-up device and a NFET pull-down device. V out = ? if V in = 0 V. C : V in V dd PFET NFET 0V 0V S D D S V out etc.) (of interconnect, capacitance Two effects of capacitor coupling 1. Time delay 2. Power increase
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Drain current in the sub-threshold region I dst ~ 100 (W/L) 10 (Vg–Vt)/S I off is the Idst measured under V g =0, and V d = V dd I off = 100 (W/L) 10 –V t /S = [100 (W/L)] / [10
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EE4353_Lecture_5_CMOS-Operation_And_Scaling - EE 4353...

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