EE4353_Lecture_7_Shallow_Junction

EE4353_Lecture_7_Shallow_Junction - EE 4353 Lecture 7...

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EE 4353 Lecture 7 Source/Drain Module Shallow Junction Professor Hsing-Huang Tseng Sep. 19, 2011
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Intel to talk of compound FinFET at 2011 IEDM EE Times 9/16/2011 5:45 AM EDT Radosavljevic's IEDM presentation on InGaAs FinFET devices with improved electrostatic performance, due to the fin shape, looks set to be in-line with that proposal. However, until now, though, the best performing III-V MOSFETs have been planar types, scaled to 10-nm gate lengths and with ultra-thin-bodies. Two key metrics are sub-threshold slope (the steeper it is, the more abruptly the device can switch) and drain-induced barrier lowering, or DIBL (the smaller it is, the less sensitive the device is to drain voltage and the more efficiently it can turn off).
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Substrate: Si High- Source Drain Gate Electrode High-k Contact Planar CMOS Scaling: Critical Modules Contact Resistance: Schottky Barrier of Silicide / Germanides Doped Ni Silicide/Germanide Schottky FETs Junction Extensions: USJ: Flash/Spike/laser anneals II, Infusion, Plasma, SS high materials selective Epi SiGe, Ge Selective Dep; Defects; strain; Eg BTBT HK/MG Scaling Ig reduction Intrinsic PID
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Source/Drain Module Shallow Junction (S/D region) Self aligned Silicide (SALICIDE) Parasitic Resistance Schottky Contact
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V t Roll-off Simple Capacitance Model As the channel length is reduced, drain to channel distance is reduced C d increases oxe d ds long t t C C V V V V ds helps V gs to invert the surface, therefore Due to built-in potential between N - channel and N + drain & source oxe d t t C C V V V 4 . 0
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EE4353_Lecture_7_Shallow_Junction - EE 4353 Lecture 7...

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