Chapter14 Timers

Chapter14 Timers - HCS12 Timers Textbook - Chapter 14 Timer...

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HCS12 Timers Textbook - Chapter 14
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Timer usage in computer systems Periodically interrupt CPU to perform tasks Sample temperature/pressure readings Generate music samples Provide accurate time delays Instead of software loops Generate pulses or periodic waveforms PWM signal for motor control Strobe pulse for an external device Determine time of an external event
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Timing functions in the HCS12 Real-time interrupt (RTI) Derived from main oscillator Periodically set flag and trigger interrupt Timer module 8 channels (TC0-TC7) of output compare/input capture functions Work with Port T pins Pulse-width modulator (PWM) Generate up to 6 PWM waveforms on Port P pins
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HCS12 Basic Timer Module (Chapter 14.2) Based on 16-bit free-running timer (TCNT) 8 channels - each uses/controls one I/O pin Pins in Port T (PT0, PT1, …, PT7) Input capture: capture time of PTn change Output compare: trigger event at designated time 16-bit pulse accumulator Count pulses on an input pin
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Main timer system block diagram. Timer count prescaler 8 channels of input capture Pulse accumulator I/O Pins Interrupt signal
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TCNT 16-bit free-running counter TCNT resets to 0000 and runs (increments) continuously Read TCNT at any time (address $0044, $0045) TCNT cannot otherwise be set TCNT clocked by system “bus” clock Bus clock = 1/2 oscillator frequency Bus clock “prescaled” by programmable divider divide by factor of 1, 2, 4, 8, 16, 32, 64, 128 Timer overflow flag sets when TCNT rolls over from $FFFF to $0000 Triggers timer overflow interrupt, if enabled
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TCNT free-running counter Prescale factor (divide by 2 PR ) Timer enable Timer overflow flag Optional reset on channel 7 output compare
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Timer overflow hardware CCR Interrupt Mask (in CPU) Timer Overflow Interrupt Enable Timer Overflow Flag
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Timer registers Timer Count Register (TCNT) Read with 16-bit load (LDX, LDY, LDD) Don’t use 8-bit loads (LDAA, LDAB) Timer System Control Register 1 (TSCR1) Enables bus clock to increment TCNT Timer System Control Register 2 (TSCR2) Enables interrupt on TCNT overflow Timer Interrupt Flag Register 2 (TFLG2) Flag indicates TCNT overflow
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Timer System Control Register 1 (TSCR1) 7 6 5 4 3 2 1 0 0 0 0 0 Timer fast flag clear all Timer stops in background mode 0 = continue running (default) Timer stops while in wait 0 = continue running (default) Timer enable 0 disables TNCT (default) 1 enables the timer TEN TSWAI TSFRZ TFFCA TSCR1 address: $0046
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Timer System Control Register 2 (TSCR2) 7 6 5 4 3 2 1 0 TOI 0 TPU TDRB TCRE PR2 PR1 PR0 Prescale Factor 000 – 1 001 – 2 010 – 4 011 – 8 100 – 16 101 – 32 110 – 64 111 - 128 Timer Overflow Interrupt Enable Timer Pull-up Resistor Enable Timer Drive Reduction Timer Counter Reset Enable 1 = reset to 0000 on output compare on channel 7 0 = TNCT runs free 1 =enable interrupt when TOF set 0 = inhibit interrupt TSCR2 address: $004D
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Chapter14 Timers - HCS12 Timers Textbook - Chapter 14 Timer...

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