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ELEC2200 HW18 M11 - Chapter 4 Sketch the circuit showing...

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ELEC 2200 Homework #18 Due Wednesday, July 20 Reading: Chapter 7.1 (Shift registers), Chapter 6.4.4 (registers) and Chapter 4 (adders, multiplexers). 1. An 8-bit adder is to compute A = A + B, where A and B are 8-bit registers. The registers are to be controlled by two signals, LDA (Load A) and LDB (Load B). A must be able to be loaded with an external number N or with the output of the adder. This is to be controlled by a signal SELA (Select A), where SELA = 0 to select N to be loaded into A, and SELA=1 to select the adder output to be loaded into A. A is loaded with one or the other of these two values whenever LDA is activated. Register A is also to be able to be asynchronously cleared (set to all 0 s) by an active- low control signal CLRA# (Clear A Bar ). Register B only needs to be able to load the external input N, when LDB is activated. For registers A and B, use the 74273 module, described in Chapter 6. For the adder, use two 7483 modules, and for the input to register A use appropriate multiplexer modules from
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Unformatted text preview: Chapter 4. Sketch the circuit, showing the modules, the above-described control signals, and their interconnections. 2. Design a 4-bit bidirectional shift register with parallel-load capability. The shift register has four parallel inputs, D3-D2-D1-D0, four outputs, Q3-Q2-Q1-Q0, two serial inputs, SHR and SHL, a clock input, and two control lines, C1-C0, that select the function to be performed, as follows. Whenever the clock activates, one of the four functions is to be performed, as selected by C1-C0. C1-C0 Function 0 0 Hold register does not change 0 1 Load the parallel inputs D3-D0 into Q3-Q0 1 0 Shift one bit to the left, with SHL shifted into Q0 1 1 Shift one bit to the right, with SHR shifted into Q3 a. Design the shift register using D flip flops, with multiplexers at their inputs. b. Redesign the shift register using JK flip flops instead of D flip flops....
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