ELEC3050 HCS12 Lab4 Digilent

ELEC3050 HCS12 Lab4 Digilent - ELEC3040/ 3050 Lab Manual...

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ELEC3040/ 3050 Lab Manual Lab 4 Revised 9/7/2011 4-1 LAB 4: INTERRUPT PROCESSING IN C INTRODUCTION The previous labs worked with simple input/output (I/O) devices using program- controlled I/O ; the programs continuously monitored each “device” to determine when to take action. The primary disadvantage of using this approach to handle I/O devices is that the CPU spends considerable amounts of time scanning devices to see if they require attention, whether or not there is any device activity. The purpose of this lab is to learn how to design C programs for the MC9S12C32 (HCS12) microcontroller to handle devices in interrupt-driven I/O mode. This allows the CPU to perform tasks other than monitoring the devices, since devices will signal the CPU via interrupt request signals when they require attention. Interrupt-driven I/O is used heavily in embedded system applications, with interrupt signals coming from external devices, data acquisition hardware, timers, etc. For this introductory lab, we will simulate the operation of two external devices by using switches to issue interrupt requests. The application program will comprise a main task, which runs continuously, and two interrupt service routines, which are executed when interrupt requests are detected. HCS12 INTERRUPTS (Review of ELEC 2220 Material) External Interrupt Pins and Interrupt Masks The HCS12 CPU has a number of built-in functions that can issue interrupt request signals, including timers, analog to digital converter, communication modules, etc. In addition to these internally-generated signals, the HCS12 has two input pins that can be used by external devices to signal interrupt requests: IRQ# (Interrupt Request on pin PE1) and XIRQ# (Non-Maskable Interrupt – on pin PE0); refer to the microcontroller pin assignments in the Lab 2 writeup. IRQ# is an active-low signal that can be configured, via bit IRQE (bit 7) of the IRQ Control Register, INTCR (shown in Figure 1), as either a level-sensitive or edge-sensitive input. If configured as level-sensitive (IRQE=0), the CPU is interrupted if and only if the line is low at the time the CPU samples it (the CPU samples all interrupt request signals at the conclusion of each executed instruction). Therefore, IRQ# must (1) be driven low to request an interrupt, (2) remain low until the CPU acknowledges the interrupt request, and then (3) return high to prevent triggering additional interrupts. Multiple interrupt sources may be connected to IRQ# , so that if two devices request interrupts simultaneously, one device may continue to hold the line low while the other is being serviced, and thus interrupt the CPU when it finishes with the first device. If IRQ# is configured as edge-sensitive (IRQE=1), then a falling edge (high-to-low transition) on the pin sets an internal flip flop, which remains set until the CPU responds. Therefore, one need not be concerned about the CPU missing the request. Since the internal flip-flop is edge triggered, the device must return
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This note was uploaded on 09/23/2011 for the course ELEC 3040 taught by Professor Staff during the Fall '08 term at Auburn University.

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ELEC3050 HCS12 Lab4 Digilent - ELEC3040/ 3050 Lab Manual...

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