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Unformatted text preview: The input/output signals are as follows: CLK : active-high clock input CLEAR* : active-low clear input L/C* : high to select load, low to select count I2,I1,I0 : parallel data inputs Q2,Q1,Q0 : parallel data outputs Your design must use D flip flops and simple logic gates, with the circuit minimized as much as possible. Submit your final schematic diagram and your design work. I2 I1 I0 Q2 Q1 Q0 CLK L/C* CLEAR*...
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- Fall '08