Project 2 - Modulo6 VHDL

Project 2 - Modulo6 VHDL - ELEC 5250/6250 Homework Project...

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ELEC 5250/6250 – Homework Project 2 Now that you have designed a gate-level structural model of a modulo-6 counter by hand, we want to (1) verify its correctness through simulation, (2) develop a behavioral model of the counter, which is where we would normally begin the design process, and (3) compare your hand-designed gate-level model with one that might be synthesized from the behavioral model by the Leonardo or Synopsys automatic synthesis tools. So, in this project you are to write two VHDL models. Model 1. Design a VHDL behavioral model of the modulo-6 counter from Homework Project 1. The model should have a single entity and architecture, and should therefore not instantiate any lower-level components. The inputs/outputs and behavior are to be identical to those of the hand-designed circuit. Use IEEE Standard 1164 data types “std_logic” and “std_logic_vector” instead of types “bit” and “bit_vector” throughout your model. Since this is a behavioral model, you may also use integers, if you wish. Model 2.
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This note was uploaded on 09/23/2011 for the course ELEC 5250 taught by Professor Staff during the Fall '08 term at Auburn University.

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