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Unformatted text preview: show me where in the simulation each of the counters functions is being verified (clearing, counting, loading). You need to convince me that all functions have been verified in the simulation. Items to submit: 1. Your original schematic from Project 1. 2. Your behavioral and structural VHDL models from Project 2, corrected as necessary. 3. Part 1: A printout of your do file. Part 2: A printout of your testbench. 4. A printout of the four annotated wave windows....
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- Fall '08