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Project 4 - VHDL Divider

Project 4 - VHDL Divider - ELEC 5250/6250 VHDL Project#4...

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ELEC 5250/6250 VHDL Project #4 First draft – Due Thursday, September 15 (for instructor feedback only – no grade) Final version, including test bench and simulation – Due Tuesday, September 20 Design a hierarchical VHDL register-transfer-level (RTL) model of a circuit that performs the arithmetic division operation on two unsigned integer numbers. A is to be an 8-bit unsigned “divisor”, and B is to be a 16-bit unsigned “dividend”. The quotient, Q, and remainder, R, are each to be 8-bit unsigned integer values. The algorithm to be implemented is to be an iterative (sequence of 8 subtract/add and shift operations) “restoring division” or “non-restoring division” algorithm (refer to various computer architecture text books for descriptions.) 1. Design four separate VHDL models: (1) register component (one common model to be instantiated for all registers), (2) the arithmetic unit, (3) the controller, and (4) a top-level model that instantiates these components.
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