ELEC 5250/6250 Project #5 – Synthesis Due Thursday, September 29, 2011 A. For the Modulo-6 counter designed previously: 1. Use “LeonardoSpectrum” to synthesize a gate-level netlist of ADK standard cells (tsmc025 technology), producing both VHDL and Verilog netlist files. 2. Repeat the structural simulation performed previously, but using the synthesized netlist, and verify that the synthesized circuit produces the same results as the behavioral model. If the results do not agree, comment on the differences. Use the previously-designed testbench to perform the simulation. Submit your simulation results for each of the following. a. Simulate the synthesized VHDL netlist. b. Repeat for the synthesized Verilog netlist. NOTE – We will save the “timing simulation” with the VITAL models and SDF file information for a future assignment. 3. Write a short comparison of the synthesized circuit and the schematic you designed by hand in the initial semester project, comparing the number of gate instances and
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