Timing Analysis - Gate-Level Timing Analysis Smith Chapter...

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Gate-Level Timing Analysis Smith Chapter 13
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Outline Gate-delay models Circuit timing constraints After Synthesis: VITAL models for gate-level simulation VHDL netlist simulation with VITAL models and Standard Delay Format (SDF) files
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Logic cell delay models “Delay” = time from the occurrence of an event until the occurrence time of a 2nd event caused by the first depends on circuit structure & technology may also depend on cell interconnects model delays with different levels of detail/accuracy may have a range of possible values (process/condition dependent) Event Event Delay
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Primitive device delay models A primitive logic gate has an intrinsic delay. model as an ideal (zero-delay) gate and a “transport delay” element. transport delay models: unit/nominal delay rise/fall delay ambiguous or min/max delay a b c Ideal gate Time delay c* t
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Unit/nominal delay Unit delay: each gate has delay of one “unit” of time. Nominal delay: delays determined separately for each type of gate (e.g., on time unit for NOR and two time units for XOR). a b c t t
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Rise/fall delay Delays for 0 to 1 and 1 to 0 transitions. t PLH (rise time): propagation delay for signal changing from low to high. t PHL (fall time): propagation delay from high to low. t PLH (rise time) t PHL (fall time) a b c
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Example: ADK tsmc035 technology nand02 cell: tP=0.537466 (ns) INV on A0(RI) to Y(FA) tP=0.810693 (ns) INV on A0(FA) to Y(RI) tP=0.421754 (ns) INV on A1(RI) to Y(FA)
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This note was uploaded on 09/23/2011 for the course ELEC 5250 taught by Professor Staff during the Fall '08 term at Auburn University.

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Timing Analysis - Gate-Level Timing Analysis Smith Chapter...

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