VHDL 1 Intro

VHDL 1 Intro - Modeling & Simulating ASIC Designs with...

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Modeling & Simulating ASIC Designs with VHDL Reference: Smith text: Chapters 10 & 12
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Hardware Description Languages VHDL = VHSIC Hardware Description Language (VHSIC = Very High Speed Integrated Circuits) Developed by DOD from 1983 – based on ADA IEEE Standard 1076-1987/1993/2002/2008 Based on the ADA language Verilog – created in 1984 by Philip Moorby of Gateway Design Automation (merged with Cadence) IEEE Standard 1364-1995/2001/2005 Based on the C language IEEE P1800 “System Verilog” in voting stage & will be merged with 1364
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Other VHDL Standards 1076.1 –1999: VHDL-AMS (Analog & Mixed-Signal Extensions) 1076.2 –1996: Std. VHDL Mathematics Packages 1076.3 -1997: Std. VHDL Synthesis Packages 1076.4 -1995: Std. VITAL Modeling Specification (VHDL Initiative Towards ASIC Libraries) 1076.6 -1999: Std. for VHDL Register Transfer Level (RTL) Synthesis 1164 -1993: Std. Multivalue Logic System for VHDL Model Interoperability
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HDLs in Digital System Design Model and document digital systems Hierarchical models System, RTL (Register Transfer Level), Gates Different levels of abstraction Behavior, structure Verify circuit/system design via simulation Automated synthesis of circuits from HDL models using a technology library output is primitive cell-level netlist (gates, flip flops, etc.)
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Anatomy of a VHDL model “Entity” describes the external view of a component “Architecture” describes the internal behavior and/or structure of the component Example: 1-bit full adder A B Cin Sum Cout Full Adder
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Example: 1-Bit Full Adder entity full_add1 is port ( -- I/O ports a: in bit; -- addend input b: in bit; -- augend input cin: in bit; -- carry input sum: out bit; -- sum output cout: out bit); -- carry output end full_add1 ; Comments follow double-dash Type of signal Signal direction (mode) Signal name I/O Port Declarations
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Port Format: name: direction data_type; Direction in - driven into the entity from an external source (can read, but not update within architecture) out - driven from within the entity (can drive but not read within architecture) inout – bidirectional; drivers both within the entity and external (can read or write within architecture) buffer – like “out” but can read and write Data_type : any scalar or aggregate signal type
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VHDL 1 Intro - Modeling & Simulating ASIC Designs with...

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