VHDL 2 Combinational

VHDL 2 Combinational - VHDL Modeling for Synthesis...

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VHDL Modeling for Synthesis Combinational Logic Circuits
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VHDL synthesis references LeonardoSpectrum HDL Synthesis Manual” Access from Leonardo “Help” menu or mgcdocs _bk_leospec.pdf Smith Text: Chapter 12 VHDL and Verilog synthesis examples Synopsys Design Compiler (DC) used for book examples Synopsys DesignVision is the GUI interface to DC
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Common types of synthesized circuits Combinational logic circuits (12.6.2 – 12.6.5) random logic (12.6.2) multiplexers (12.6.3) decoders (12.6.4) Arithmetic functions (12.6.5, 12.6.9, 12.6.10) Sequential logic (registers) (12.6.6) synchronous & asynchronous inputs Shift registers (12.6.8) Finite state machines (12.7, 12.7.2) Memory synthesis (12.8, 12.8.2)
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Combinational logic -- Specify behavior via concurrent signal assignments entity Gates is port (a, b,c: in BIT; d: out BIT); end Gates; architecture behavior of Gates is signal e: BIT; Begin -- concurrent signal assignment statements e <= (a and b) xor (not c); -- synthesize gate-level ckt d <= a nor b and (not e); -- in target technology end;
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VHDL “Process” Construct Allows conventional programming language methods to describe circuit behavior Supported language constructs (“sequential statements”) – only allowed within a process: variable assignment if-then-else (elsif) case statement while (condition) loop for (range) loop
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Process Format [label:] process ( sensitivity list ) declarations begin sequential statements end process; Process statements executed once at start of simulation Process halts at “end” until an event occurs on a signal in the “sensitivity list”
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Combinational logic via process -- All signals referenced in process must be in the sensitivity list. entity And_Good is port (a, b: in BIT; c: out BIT); end And_Good; architecture Synthesis_Good of And_Good is begin process (a,b) -- gate sensitive to events on (a, b) begin c <= a and b; -- c updated on a or b “events” end process; end;
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Combinational logic via process -- This example produces unexpected results. entity And_Bad is port (a, b: in BIT; c: out BIT); end And_Bad; architecture Synthesis_Bad of And_Bad is begin process (a) -- this should be process (a, b) begin c <= a and b; -- will not react to changes in b end process; end Synthesis_Bad; -- synthesis tool may generate a flip flop, triggered by signal a
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Structural architecture example (no “behavior” specified) architecture structure of full_add1 is component xor -- declare component to be used port (x,y: in bit; z: out bit); end component; for all: xor use entity work.xor(eqns); -- if multiple arch’s signal x1: bit; -- signal internal to this component begin G1: xor port map (a, b, x1); -- instantiate 1 st xor gate G2: xor port map (x1, cin, sum); -- instantiate 2 nd xor gate add circuit for carry output end;
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architecture Netlist of Half_Adder is -- declare all components to be used
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This note was uploaded on 09/23/2011 for the course ELEC 5250 taught by Professor Staff during the Fall '08 term at Auburn University.

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VHDL 2 Combinational - VHDL Modeling for Synthesis...

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