VHDL 3 Sequential

VHDL 3 Sequential - VHDL Modeling for Synthesis Sequential...

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VHDL Modeling for Synthesis Sequential Logic Circuits
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VHDL “Process” Construct Allows conventional programming language methods to describe circuit behavior Supported language constructs (“sequential statements”) – only allowed within a process: variable assignment if-then-else (elsif) case statement while (condition) loop for (range) loop
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Process Format [label:] process ( sensitivity list ) declarations begin sequential statements end process; Process statements executed once at start of simulation Process halts at “end” until an event occurs on a signal in the “sensitivity list”
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Modeling sequential behavior -- Edge-triggered flip flop/register entity DFF is port (D,CLK: in bit; Q: out bit); end DFF; architecture behave of DFF is begin process(clk) -- “process sensitivity list” begin if (clk’event and clk=‘1’) then Q <= D after 1 ns; end if; end process; end; Process statements executed sequentially (sequential statements) clk’event is an attribute of signal clk which is TRUE if an event has occurred on clk at the current simulation time D Q CLK
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Edge-triggered flip-flop Alternative methods for specifying clock process (clk) begin if rising_edge(clk) then -- std_logic_1164 function Q <= D ; end if; end process; Leonardo also recognizes not clk’stable as equivalent to clk’event
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Alternative to sensitivity list process -- no “sensitivity list” begin wait on clk; -- suspend process until event on clk if (clk=‘1’) then Q <= D after 1 ns; end if; end process; Other “wait” formats: wait until (clk’event and clk=‘1’) wait for 20 ns; This format does not allow for asynchronous controls Process executes endlessly if no sensitivity list or wait statement! D Q CLK
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Level-Sensitive D latch vs. D flip-flop entity Dlatch is port (D,CLK: in bit; Q: out bit); end Dlatch; architecture behave of Dlatch is begin process(D, clk) begin if (clk=‘1’) then Q <= D after 1 ns; end if; end process; end; Latch, Q changes whenever the latch is enabled by CLK=‘1’ (rather than edge-triggered) D Q CLK
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model (not gate-level) entity Reg8 is port (D: in bit_vector(0 to 7); Q: out bit_vector(0 to 7); LD: in bit); end Reg8; architecture behave of Reg8 is begin process(LD) begin if (LD’event and LD=‘1’) then
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VHDL 3 Sequential - VHDL Modeling for Synthesis Sequential...

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