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VHDL 6 Testbench - VHDL Simulation Testbench Design The...

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VHDL Simulation Testbench Design
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The Test Bench Concept
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Project simulations 1. Behavioral/RTL – verify functionality Model in VHDL/Verilog Drive with “force file” or testbench 2. Post-Synthesis Synthesized gate-level VHDL/Verilog netlist Technology-specific VHDL/Verilog gate-level models Optional SDF file (from synthesis) for timing Drive with same force file/testbench as in (1) 3. Post-Layout Netlist back-annotated with extracted capacitances for accurate delays
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Example: modulo-7 counter VHDL Model (modulo7.vhd) Create working library: vlib work Map the lib name: vmap work work Compile: vcom modulo7.vhd Simulate: vsim modulo7(behave) Simulation-control Modelsim “macro” file (mod7.do) Testbench (VHDL or Verilog) ModelSim results List(table) and/or Waveform (logic analyzer)
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-- modulo7.vhd parallel-load modulo-7 synchronous counter library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity modulo7 is port(reset,count,load,clk: in std_logic; I: in std_logic_vector(2 downto 0); Q: out std_logic_vector(2 downto 0)); end modulo7; architecture Behave of modulo7 is signal Q_s: unsigned(2 downto 0); begin process (reset,clk) begin if (reset='0') then Q_s <= "000"; elsif (clk'event and (clk='1')) then if (count = '1') and (Q_s = "110") then Q_s <= "000"; elsif (count='1') then Q_s <= Q_s + 1; elsif (load='1') then Q_s <= UNSIGNED(I); end if; end if; end process; Q<=STD_LOGIC_VECTOR(Q_s); end Behave;
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Test stimulus: Modelsim “do” file: mod7.do add wave /clk /reset /count /load add wave -hex /I /Q add list /clk /reset /count /load add list -hex /I /Q force /clk 0 0 ns, 1 20 ns -repeat 40 ns force /I 101 0 ns, 011 400 ns force /reset 1 0 ns, 0 10 ns, 1 20 ns force /count 0 0 ns, 1 90 ns, 0 490 ns force /load 0 0 ns, 1 30 ns, 0 70 ns
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