VHDL 7 Synthesis with Leonardo

VHDL 7 Synthesis with Leonardo - Automated Synthesis from...

Info iconThis preview shows pages 1–12. Sign up to view the full content.

View Full Document Right Arrow Icon
Automated Synthesis from HDL models Leonardo (Mentor Graphics), Design Compiler (Synopsys)
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
ASIC Design Flow Behavioral Model VHDL/Verilog Gate-Level Netlist Transistor-Level Netlist Physical Layout Map/Place/Route DFT/BIST & ATPG Verify Function Verify Function Verify Function & Timing Verify Timing DRC & LVS Verification IC Mask Data/FPGA Configuration File Standard Cell IC & FPGA/CPLD Synthesis Test vectors Full-custom IC
Background image of page 2
Project directory structure /design /src /syn /sim /layout /work /adk do files synthesis script logs/reports design database netlist (.v .vhd) sdf, sdc, pow files .v .vhd Physical layout files
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Automated synthesis Leonardo Spectrum, Synopsys Design Compiler HDL Behavioral/RTL Models FPGA ASIC Technology Synthesis Libraries Technology- Specific Netlist Design Constraints VHDL, Verilog, SDF, EDIF, XNF Leonardo: Level 1 – FPGA Level 2 – FPGA + Timing Level 3 – FPGA + ASIC or ASIC only
Background image of page 4
Leonardo – ASIC synthesis flow
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Synthesis design flow
Background image of page 6
Synthesis steps 1. Load technology library into database 2. Analyze design Load HDL models into database, check for synthesizable models 3. Elaborate design Technology-independent circuit (random & structured logic) 4. Specify design constraints (timing, area) 5. Compile/optimize design Optimize for the loaded technology library Repeat as necessary to meet constraints 6. Generate technology-specific netlist(s) 7. Generate simulation timing data (SDF file) 8. Generate reports (cells, area, timing)
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
LeonardoSpectrum Documentation To access documentation (Linux): In .bashrc file: export EXEMPLAR=/linux_apps/mentor/LeonardoSpectrum/2011a From command line: mgcdocs $EXEMPLAR/doc/_bk_leospec.pdf –pdf Main Documents: User’s manual Reference Manual (Command summaries) HDL Synthesis Manual (VHDL/Verilog for synthesis) Synthesis and Technology Manual (ASIC/FPGA-specific)
Background image of page 8
Invoking LeonardoSpectrum 1. Invoke command line version: spectrum Only “Spectrum” currently available for Linux To execute command file after startup: spectrum –file mycommands.tcl 2. To invoke GUI version: leonardo Not available in Linux version Last versions were SunOS and Windows XP No Windows 7 version
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
LeonardoSpectrum synthesis example Load technology library: tsmc035 (ASIC) Load design file: modulo7.vhd Specify constraints: clock freq, delays, etc. Optimization: effort, performance vs. area Write synthesized netlist output(s): modulo7_0.vhd : VHDL netlist for ModelSim & DFT modulo7.v : Verilog netlist for import into DA-IC modulo7.sdf : For ModelSim to study timing modulo7.edf : EDIF netlist for 3 rd party tools modulo7.xnf : Xilinx netlist for Xilinx ISE
Background image of page 10
Behavioral model to be synthesized -- modulo-7 counter with asynchronous reset and synchronous load/count library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity modulo7 is port( count, load, reset, clk: in std_logic; I: in unsigned(2 downto 0);
Background image of page 11

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 12
This is the end of the preview. Sign up to access the rest of the document.

Page1 / 44

VHDL 7 Synthesis with Leonardo - Automated Synthesis from...

This preview shows document pages 1 - 12. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online