VHDL 8 Multiplier Nelson

VHDL 8 Multiplier Nelson - System Example: 8x8 multiplier...

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System Example: 8x8 multiplier adder (ADR) multiplicand (M) accumulator (A) multiplier (Q) controller (C) Start Clock Done Input Bus Output Bus
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Multiply Algorithm A <- 0 M <- INBUS CNT <- 0 Q <- INBUS A <- A + M Q(7) A:Q <- right shift CNT <- CNT + 1 CNT A(0) <- sign OUTBUS <= A OUTBUS <= Q 1 0 <8 8 IN1 IN2 ADD SHIFT SIGN OUT1 OUT2 START DONE <- 1 HALT 0 1
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Multiplier – Top Level entity multiplier is port (INBUS: in bit_vector(0 to 7); OUTBUS: out bit_vector(0 to 7); CLOCK: in bit; START: in bit; DONE: out bit); end multiplier; architecture structure of multiplier is [component declarations go here] -- internal signals to interconnect components signal AR, MR, QR, AD, Ain: bit_vector(0 to 7); signal AMload, AMadd, Qload, AQshift, AQoutEn, AQoutSel: bit; signal SignLd: bit;
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begin -- Output multiplexer OUTBUS <= AR when AQoutEn = '1' and AQoutSel = '0' else QR when AQoutEn = '1' and AQoutSel = '1' else "00000000"; Ain(0) <= AD(0) when AMadd = '1' else MR(0) xor QR(7); Ain(1 to 7) <= AD(1 to 7); M: mreg port map (INBUS, MR, AMload); Q: Qreg port map (INBUS, QR, AR(7), Qload, SignLd, AQshift); A: areg port map (Ain, AR, AMadd, SignLd, AQshift, AMload); ADR: adder port map (AR, MR, AD); C: mctrl port map (START, CLOCK, QR(7), AMload, AMadd, Qload, AQshift, SignLd, AQoutEn, AQoutSel, DONE);
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This note was uploaded on 09/23/2011 for the course ELEC 5250 taught by Professor Staff during the Fall '08 term at Auburn University.

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VHDL 8 Multiplier Nelson - System Example: 8x8 multiplier...

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