VHDL 9 VITAL SDF - Gate-Level Timing Analysis VITAL Models...

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Gate-Level Timing Analysis VITAL Models & SDF Files
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Timing simulation with VHDL models Synthesized structural models comprise cells from a library (ADK library, for example) Each library cell has been characterized to determine delays, constraints, etc. Most current libraries represent timing information using the VITAL standard VHDL Initiative Toward ASIC Libraries IEEE Standard 1076.4 Synthesis tools create a Standard Delay Format (SDF) file of timing data for each cell in the design for use with VITAL models SDF = IEEE Standard 1497 Designed for back-annotation of netlists with delay data
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Example The modulo 7 counter was synthesized using one of the technologies in the ADK The next slides show a VITAL model of a D flip flop from the library. The following slides contain a partial SDF file, showing the timing parameters extracted for a couple of gates in the synthesized design
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library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.VITAL_Primitives.all; -- Primitive logic functions use IEEE.VITAL_Timing.all; -- Delay/Constraint calculation func’s entity dff is generic ( tipd_CLK : VitalDelayType01Z := VitalZeroDelay01Z; tipd_D : VitalDelayType01Z := VitalZeroDelay01Z; tpd_CLK_Q : VitalDelayType01Z := VitalZeroDelay01Z; tpd_CLK_QB : VitalDelayType01Z := VitalZeroDelay01Z; tsetup_D_CLK_noedge_posedge : VitalDelayType := 0 ns; thold_D_CLK_noedge_posedge : VitalDelayType := 0 ns; tpw_CLK_posedge : VitalDelayType := 0 ns; tpw_CLK_negedge : VitalDelayType := 0 ns; TimingChecksOn : BOOLEAN := TRUE; InstancePath : STRING := "*“ ); -- VitalDelayType01Z = delays for 0-1,1-0,0-Z,1-Z,Z-0,Z-1 changes VITAL model of a D flip flop Continued
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port ( D : in STD_LOGIC; CLK : in STD_LOGIC; Q : out STD_LOGIC; QB : out STD_LOGIC ); attribute VITAL_LEVEL0 of dff : entity is TRUE; end dff; architecture dff_arch of dff is attribute VITAL_LEVEL1 of dff_arch : architecture is TRUE; signal CLK_ipd : STD_LOGIC := 'X'; signal D_ipd : STD_LOGIC := 'X'; Continued DFF model (continued)
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WireDelay : Block begin -- Input wire delays VitalWireDelay (CLK_ipd, CLK, tipd_CLK); VitalWireDelay (D_ipd, D, tipd_D); end Block; VitalBehavior : Process (CLK_ipd, D_ipd) VARIABLE Tviol_0 : X01 := '0'; VARIABLE SetupHoldInfo_0 : VitalTimingDataType := VitalTimingDataInit; VARIABLE Pviol_0 : X01 := '0'; VARIABLE PeriodDataInfo_0 : VitalPeriodDataType := VitalPeriodDataInit; VARIABLE Violation_0 : X01 := '0'; VARIABLE PrevData_0 : STD_LOGIC_VECTOR(0 to 2); VARIABLE Results_0 : STD_LOGIC_VECTOR(0 to 2); DFF model (continued) Continued
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This note was uploaded on 09/23/2011 for the course ELEC 5250 taught by Professor Staff during the Fall '08 term at Auburn University.

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VHDL 9 VITAL SDF - Gate-Level Timing Analysis VITAL Models...

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