VHDL Example Multiplier Smith

VHDL Example Multiplier Smith - VHDL Modeling for Synthesis...

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VHDL Modeling for Synthesis Design Examples - Multiplier
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4-bit multiplier (hierarchical design) (Smith Chap. 10.2)
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1-bit full adder entity Full_Adder is generic (TS : TIME := 0.11 ns; TC : TIME := 0.1 ns); port (X, Y, Cin: in BIT; Cout, Sum: out BIT); end Full_Adder; architecture Behave of Full_Adder is begin Sum <= X xor Y xor Cin after TS; Cout <= (X and Y) or (X and Cin) or (Y and Cin) after TC; end; X Sum Y Cin Cout
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8-bit adder - entity -- Cascade 8 1-bit adders for 8-bit adder entity Adder8 is port (A, B: in BIT_VECTOR(7 downto 0); Cin: in BIT; Cout: out BIT; Sum: out BIT_VECTOR(7 downto 0)); end Adder8;
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architecture Structure of Adder8 is component Full_Adder -- declare component to be used port (X, Y, Cin: in BIT; Cout, Sum: out BIT); end component; signal C: BIT_VECTOR(7 downto 0); begin Stages: for i in 7 downto 0 generate LowBit: if i = 0 generate FA: Full_Adder port map (A(0),B(0),Cin,C(0),Sum(0)); end generate; OtherBits: if i /= 0 generate FA :Full_Adder port map (A(i),B(i),C(i-1),C(i),Sum(i)); end generate; end generate; Cout <= C(7); end;
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entity DFFClr is generic(TRQ : TIME := 2 ns; TCQ : TIME := 2 ns); port (CLR, CLK, D : in BIT; Q, QB : out BIT); end; architecture Behave of DFFClr is signal Qi : BIT; begin QB <= not Qi; Q <= Qi; process (CLR, CLK) begin if CLR = '1' then Qi <= '0' after TRQ; elsif CLK'EVENT and CLK = '1' then Qi <= D after TCQ; end if; end process; end; CLR Q QN D CLK
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entity Register8 is port (D : in BIT_VECTOR(7 downto 0); Clk, Clr: in BIT ; Q : out BIT_VECTOR(7 downto 0)); end; architecture Structure of Register8 is component DFFClr port (Clr, Clk, D : in BIT; Q, QB : out BIT); end component; begin STAGES: for i in 7 downto 0 generate FF: DFFClr port map (Clr, Clk, D(i), Q(i), open); end generate; end; CLR Q QN D CLK 8 8
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generic (TPD : TIME := 1 ns); port (A, B : in BIT_VECTOR (7 downto 0); Sel : in BIT := '0'; Y : out BIT_VECTOR (7 downto 0)); End Mux8; architecture Behave of Mux8 is begin Y <= A after TPD when Sel = '1' else B after TPD; end; A B 8 8 8
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VHDL Example Multiplier Smith - VHDL Modeling for Synthesis...

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