ARM LPC2292 Interrupts

ARM LPC2292 Interrupts - From ARM and LPC2292 references....

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Unformatted text preview: From ARM and LPC2292 references. ARM and LPC2292 Operating Modes & Interrupt Handling ARM operating modes User : unprivileged mode under which most tasks run FIQ : entered when a high priority (fast) interrupt is raised IRQ : entered when a low priority (normal) interrupt is raised Supervisor : entered on reset and when a Software Interrupt instruction (SWI) is executed Abort : used to handle memory access violations Undef : used to handle undefined instructions System : privileged mode using the same registers as user mode ARM Operating Modes CPSR[4:0] Mode Use Registers Vector Address 10000 User Normal user code User 0x00000000 10001 FIQ Fast interrupt _fiq 0x00000004 10010 IRQ Standard interrupt _irq 0x00000008 10011 SVC Software interrupt _svc 0x0000000C 10111 Abort Memory faults _abt 0x00000010 11011 Undef Undefined instruction _und 0x00000018 11111 System Privileged O/S task user 0x0000001C CPSR = Current Processor Status Register FIQ IRQ SVC Undef Abort User Mode Current Visible Registers Banked out Registers FIQ IRQ SVC Undef Abort Current Visible Registers Banked out Registers User IRQ SVC Undef Abort r8 r9 r10 r11 r12 FIQ Mode IRQ Mode Current Visible Registers Banked out Registers User FIQ SVC Undef Abort Undef Mode Current Visible Registers Banked out Registers User FIQ IRQ SVC Abort SVC Mode r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers User FIQ IRQ Undef Abort Abort Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 ( sp ) r14 (lr) spsr Current Visible Registers Banked out Registers...
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This note was uploaded on 09/23/2011 for the course ELEC 6260 taught by Professor Nelson,v during the Summer '08 term at Auburn University.

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ARM LPC2292 Interrupts - From ARM and LPC2292 references....

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