Chapter2 ARM - ARM Processor ARM = Advanced RISC Machines,...

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ARM = Advanced RISC Machines, Ltd. ARM licenses IP to other companies (ARM does not fabricate chips) 2005: ARM had 75% of embedded RISC market, with 2.5 billion processors ARM available as microcontrollers, IP cores, etc. www.arm.com Based on Lecture Notes by Wayne Wolf ARM Processor
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ARM instruction set - outline Based on Lecture Notes by Wayne Wolf ARM versions. ARM assembly language. ARM programming model. ARM memory organization. ARM data operations. ARM flow of control.
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ARM versions Based on Lecture Notes by Wayne Wolf ARM architecture has been extended over several versions. We will concentrate on ARM7. ARM9 – includes “Thumb” instruction set ARM10 – for multimedia (graphics, video, etc.) ARM11 – high performance + Jazelle (Java) SecurCore – for security app’s (smart cards) Cortex – Optimized for embedded app’s StrongARM – portable comm. devices
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Architecture Revisions Based on Lecture Notes by Wayne Wolf
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RISC CPU Characteristics Based on Lecture Notes by Wayne Wolf 32-bit load/store architecture Fixed instruction length Fewer/simpler instructions Limited addressing modes, operand types Simpler design easier to speed up, pipeline & scale
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ARM assembly language Based on Lecture Notes by Wayne Wolf Fairly standard assembly language: LDR r0,[r8] ; a comment label ADD r4,r0,r1 ;r4=r0+r1 destination source/left source/right
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ARM programming model Based on Lecture Notes by Wayne Wolf r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 (PC) CPSR 31 0 N Z C V Some registers (r13,r14) change during exceptions 16 32-bit general-purpose registers Current Processor Status Register Program Counter
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CPSR Current Processor Status Register Based on Lecture Notes by Wayne Wolf N Z C V I F T M 4 M 3 M 2 M 1 M 0 31 30 29 28 7 6 5 4 3 2 1 0 ALU Flags IRQ disable FIQ disable Thumb/ARM mode Processor Mode 10000 – User 10001 – FIQ 10010 – IRQ 10011 – Supervisor (SWI) 10111 – Abort D/I mem’y 11001 – Undefined instr. 11111 - System Must be in a “privileged” mode to change the CPSR MRS rn,CPSR MSR CPSR,rn
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Register Set Based on Lecture Notes by Wayne Wolf
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Endianness Based on Lecture Notes by Wayne Wolf Relationship between bit and byte/word ordering defines “endianness”: byte 3 byte 2 byte 1 byte 0 byte 0 byte 1 byte 2 byte 3 bit 31 bit 0 bit 0 bit 31 little-endian (default) big-endian
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ARM data types Based on Lecture Notes by Wayne Wolf Word is 32 bits long. Word can be divided into four 8-bit bytes. ARM addresses can be 32 bits long. Address refers to byte. Address 4 starts at byte 4. Can be configured at power-up as either little- or bit- endian mode.
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Based on Lecture Notes by Wayne Wolf Every arithmetic, logical, or shifting operation can set CPSR bits: N (negative), Z (zero), C (carry), V (overflow) Examples: -1 + 1 = 0: NZCV = 0110. 2
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This note was uploaded on 09/23/2011 for the course ELEC 6260 taught by Professor Nelson,v during the Summer '08 term at Auburn University.

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Chapter2 ARM - ARM Processor ARM = Advanced RISC Machines,...

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