Chapter 3 - CPUs
Beyond the instruction set:
Input and output.
Busy-Wait and Interrupt-Driven
Supervisor mode, exceptions, traps.
Input/output on the LPC2292
I/O ports
Busy-wait programming
Interrupt processing
UART
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I/O devices
Often includes some non-digital component.
Typical digital interface to CPU:
CPU
status
reg
data
reg
mechanism
Example: LPC2292 UART
Universal asynchronous receiver transmitter
(
UART
) : provides
serial communication.
UARTs are integrated into most microcontrollers
Two UART modules on LPC2292
Allows many communication parameters to be programmed.
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Asynchronous serial communication
Characters are transmitted separately:
time
bit 0
bit 1
P
no
char
start
stop
...
bit n-1
optional
parity bit
n data bits
LPC2292 UART CPU interface
CPU
UART
status
(8 bit)
data
(8 bit)
serial
port
xmit/
rcv
control
Baud
Rate gen