Chapter3 IO - Chapter 3 CPUs Beyond the instruction set...

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Chapter 3 - CPUs Beyond the instruction set: Input and output. Busy-Wait and Interrupt-Driven Supervisor mode, exceptions, traps. Input/output on the LPC2292 I/O ports Busy-wait programming Interrupt processing UART
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I/O devices Often includes some non-digital component. Typical digital interface to CPU: CPU status reg data reg mechanism
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Example: LPC2292 UART Universal asynchronous receiver transmitter ( UART ) : provides serial communication. UARTs are integrated into most microcontrollers Two UART modules on LPC2292 Allows many communication parameters to be programmed.
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Asynchronous serial communication Characters are transmitted separately: time bit 0 bit 1 P no char start stop ... bit n-1 optional parity bit n data bits
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LPC2292 UART CPU interface CPU UART status (8 bit) data (8 bit) serial port xmit/ rcv control Baud Rate gen
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UART “Line Control Register” Number of bits per character (5,6,7,8 bits). Enable/disable parity generation/checking. Type of parity bit: Even, Odd, Stuck-0, Stuck-1. Length of stop bit (1, 2 bits).
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This note was uploaded on 09/23/2011 for the course ELEC 6260 taught by Professor Nelson,v during the Summer '08 term at Auburn University.

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Chapter3 IO - Chapter 3 CPUs Beyond the instruction set...

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