Chapter3 Memory

Chapter3 Memory - CPUs Chapter 3.5 Caches. Memory...

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Unformatted text preview: CPUs Chapter 3.5 Caches. Memory management. Caches and CPUs CPU cache controller cache main memory data data address data address Cache operation Many main memory locations are mapped onto one cache entry. May have caches for: instructions; data; data + instructions ( unified ). Memory access time is no longer deterministic. Depends on hits and misses Terms Cache hit : required location is in cache. Cache miss : required location is not in cache. Working set : set of locations used by program in a time interval. Types of misses Compulsory ( cold ): location has never been accessed. Capacity : working set is too large. Conflict : multiple locations in working set map to same cache entry fighting for the same cache location Cache miss penalty : added time due to a cache miss. Cache performance benefits Keep frequently-accessed locations in fast cache. Cache retrieves more than one word at a time. Sequential accesses are faster after first access. Memory system performance h = cache hit rate. t cache = cache access time, t mai n = main memory access time. Average memory access time: t av = ht cache + (1-h)(t cache +t main ) :look-through t av = ht cache + (1-h)t main :look-aside Multiple levels of cache CPU L1 cache L2 cache Multi-level cache access time h 1 = cache hit rate....
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Chapter3 Memory - CPUs Chapter 3.5 Caches. Memory...

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