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Chapter3 Memory - CPUs Chapter 3.5 Caches Memory management...

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CPUs – Chapter 3.5 Caches. Memory management.
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Caches and CPUs CPU cache controller cache main memory data data address data address
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Cache operation Many main memory locations are mapped onto one cache entry. May have caches for: instructions; data; data + instructions ( unified ). Memory access time is no longer deterministic. Depends on “hits” and “misses”
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Terms Cache hit : required location is in cache. Cache miss : required location is not in cache. Working set : set of locations used by program in a time interval.
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Types of misses Compulsory ( cold ): location has never been accessed. Capacity : working set is too large. Conflict : multiple locations in working set map to same cache entry – fighting for the same cache location Cache miss penalty : added time due to a cache miss.
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Cache performance benefits Keep frequently-accessed locations in fast cache. Cache retrieves more than one word at a time. Sequential accesses are faster after first access.
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Memory system performance h = cache hit rate. t cache = cache access time, t mai n = main memory access time. Average memory access time: t av = ht cache + (1-h)(t cache +t main ) :look-through t av = ht cache + (1-h)t main :look-aside
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Multiple levels of cache CPU L1 cache L2 cache
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Multi-level cache access time h 1 = cache hit rate.
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