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Chapter4 Buses Memory - CPU Buses Mechanism for...

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CPU Buses Mechanism for communication with memories and I/O devices Bus components: signal wires with designated functions protocol for data transfers electrical parameters (voltage, current, capacitance, etc.) physical design (connectors, cables, etc.)
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CPU Bus Types Synchronous vs. Asynchronous Sync: all op’s synchronized to a clock Async: devices signal each other to indicate start/stop of operations May combine sync/async (80x86 “Ready” signal) Data transfer types: Processor to/from memory Processor to/from I/O device I/O device to/from memory (DMA)
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Hierarchical Bus Architecture CPU Cache Local controller Main Memory System bridge USB Controller Expansion USB LAN Controller Disk Controller Video Controller USB Device IDE/SCSI Mouse/ Keyboard Main Memory
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LPC2292 on-chip & external memory buses
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Typical bus data rates Source: Peter Cheung “Computer Architecture & Systems Course Notes”
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