Chapter4 Buses Memory

Chapter4 Buses - CPU Buses Mechanism for communication with memories and I/O devices Bus components signal wires with designated functions protocol

Info iconThis preview shows pages 1–25. Sign up to view the full content.

View Full Document Right Arrow Icon
CPU Buses Mechanism for communication with memories and I/O devices Bus components: signal wires with designated functions protocol for data transfers electrical parameters (voltage, current, capacitance, etc.) physical design (connectors, cables, etc.)
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
CPU Bus Types Synchronous vs. Asynchronous Sync: all op’s synchronized to a clock Async: devices signal each other to indicate start/stop of operations May combine sync/async (80x86 “Ready” signal) Data transfer types: Processor to/from memory Processor to/from I/O device I/O device to/from memory (DMA)
Background image of page 2
Hierarchical Bus Architecture CPU Cache Local controller System bridge USB Controller Expansion USB LAN Controller Disk Controller Video Controller USB Device IDE/SCSI Mouse/ Keyboard Main Memory
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
LPC2292 on-chip & external memory buses
Background image of page 4
Typical bus data rates Source: Peter Cheung “Computer Architecture & Systems Course Notes”
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Bus protocols © 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Bus protocol determines how devices communicate. Devices on the bus go through sequences of states. Protocols are specified by state machines, one state machine per actor in the protocol. May contain asynchronous logic behavior.
Background image of page 6
Microprocessor busses © 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. Clock provides synchronization. R/W is true when reading (R/W’ is false when reading). Address is a-bit bundle of address lines. Data is n-bit bundle of data lines. Data ready signals when n-bit data is ready.
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Timing diagrams © 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed.
Background image of page 8
Bus read © 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed.
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
State diagrams for bus read © 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. CPU device Get data Done Adrs Wait See ack Send data Release ack Adrs Ack start
Background image of page 10
Bus wait state © 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed.
Background image of page 11

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Bus burst read © 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed.
Background image of page 12
Bus multiplexing © 2008 Wayne Wolf Overheads for Computers as Components 2 nd ed. CPU adrs device data adrs data enable Adrs enable
Background image of page 13

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Memory device organization Size. Address width. n = r + c Aspect ratio. Data width d. Memory array n r c d
Background image of page 14
Types of memory ROM: Mask-programmable. Flash programmable. RAM: DRAM. SRAM.
Background image of page 15

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
SRAM vs. DRAM SRAM: Faster. Easier to integrate with logic. Higher power consumption. DRAM: Denser. Must be refreshed.
Background image of page 16
Typical generic SRAM SRAM CE’ R/W’ Adrs Data •May have OE’ and WE’ instead of R/W’ •For multi-byte Data, may have byte-select signals
Background image of page 17

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
512K x 16 SRAM (on uCdragon board)
Background image of page 18
Generic SRAM timing time CE’ R/W’ Adrs Data read write From SRAM From CPU
Background image of page 19

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
ISSI IS61LV51216 SRAM read cycle
Background image of page 20
ISSI IS61LV51216 SRAM timing
Background image of page 21

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Generic DRAM device DRAM CE’ R/W’ Adrs Data RAS’ CAS’
Background image of page 22
Generic DRAM timing time CE’ R/W’ RAS’ CAS’ Adrs Data row adrs col adrs data
Background image of page 23

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Page mode access time CE’ R/W’ RAS’ CAS’ Adrs Data row adrs col adrs data col adrs col adrs data data
Background image of page 24
Image of page 25
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 09/23/2011 for the course ELEC 6260 taught by Professor Nelson,v during the Summer '08 term at Auburn University.

Page1 / 72

Chapter4 Buses - CPU Buses Mechanism for communication with memories and I/O devices Bus components signal wires with designated functions protocol

This preview shows document pages 1 - 25. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online