{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

Chapter8 SPI LPC2292 - Serial Peripheral Interface(SPI...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
Serial Peripheral Interface (SPI) Synchronous serial data transfers multipoint serial communication between a “master” and a “slave” device clock permits faster data rates than async communications (framing unnecessary) signals” clock, two data, “slave select” master controls all data transfers: transmit synchronization clock activate slave select signal all device data registers effectively linked into a single “shift register”
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Single master, single-slave SPI connections Slave Master Clock Gen MOSI MISO SCK Slave Select SS CS SCLK – serial clock, generated by the master MOSI – master output/slave input MISO – master input/slave output SS – slave select/enable signal Shift register Shift register
Background image of page 2
Single master, multiple slave SPI implementation Slave-selects
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon