Chapter8 SPI LPC2292

Chapter8 SPI LPC2292 - Serial Peripheral Interface (SPI)...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
Serial Peripheral Interface (SPI) Synchronous serial data transfers multipoint serial communication between a “master” and a “slave” device clock permits faster data rates than async communications (framing unnecessary) signals” clock, two data, “slave select” master controls all data transfers: transmit synchronization clock activate slave select signal all device data registers effectively linked into a single “shift register”
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Single master, single-slave SPI connections Slave Master Clock Gen MOSI MISO SCK Slave Select SS CS SCLK – serial clock, generated by the master MOSI – master output/slave input MISO – master input/slave output SS – slave select/enable signal Shift register Shift register
Background image of page 2
Single master, multiple slave SPI implementation Slave-selects
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Single master, multiple slave SPI implementation – daisy chained • Dout of one device connected to Din of next (creates a single shift register) • All devices selected concurrently by the Master
Background image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 09/23/2011 for the course ELEC 6260 taught by Professor Nelson,v during the Summer '08 term at Auburn University.

Page1 / 22

Chapter8 SPI LPC2292 - Serial Peripheral Interface (SPI)...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online