33 TL circuits with half and quarterwave trans
formers
•
Last lecture we established that phasor solutions of telegrapher’s equa
tions for TL’s in sinusoidal steadystate can be expressed as
V
(
d
)=
V
+
e
jβd
+
V

e

jβd
and
I
(
d
)=
V
+
e
jβd

V

e

jβd
Z
o
in a new coordinate system shown in the margin.
l
Input
port
Z
o

l
z
0
0
l
d
LOAD
GENERATOR,
Circuit
Z
L
=
R
L
+
jX
L
I
(
d
)
V
(
d
)
+

By convention the load is located on the right at
z
=0=
d
, and the
TL input connected to a generator or some source circuit is shown on
the left at
d
=
l
.
We have replaced the short termination of the previous lecture with an
arbitrary load impedance
Z
L
=
R
L
+
jX
L
.
In this lecture we will discuss sinusoidal steadystate TL cir
cuit problems having arbitrary reactive loads but with line
lengths
l
constrained to be integer multiples of
λ
4
(at the op
eration frequency).
The constraint will be lifted next lecture when we will de
velop the general analysis tools for sinusoidal steadystate TL
circuits.
1
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In the TL circuit shown in the margin an arbitrary load
Z
L
is connected
to a TL of length
l
=
λ
2
at the source frequency.
Given that
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 Fall '08
 Kim
 Alternating Current, Input impedance, The Circuit, Impedance matching, Impedance bridging, jIL Zo

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