Lecture3 - ECE-L304 Lecture 3 Review of Step 2 Introduction...

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ECE-L304 Lecture 3 Review of Step 2 Introduction to Logic Analyzer Tech Notes
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ECE-L304 Lecture 3 2 Step 2 Lab 8-pin header Data Bus Test Port Resistor Array LED Array Components Self-Clocked ADC
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ECE-L304 Lecture 3 3 Questions What is the frequency bandwidth of human speech? What is the minimum sampling rate for digital recording of speech? How many internal clock cycles does this ADC need to take one sample? What is the maximum internal clock rate? What clock rate to you want? Defend this choice. What values of R and C give you this rate?
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ECE-L304 Lecture 3 4 Step 2 Review Floorplan is complete Remember that this is a physical representation of where the parts will go Keep a drawing in your lab notebook for reference ADC clock components are chosen Boards and parts kits are distributed Measurements are in progress
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ECE-L304 Lecture 3 5 Step 2 Review ADC Performance Measurements Table of dc tests Observation of performance on logic analyzer Comparison of predicted and measured timing Report writing in progress Due next week
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ECE-L304 Lecture 3 6 Step 2 Review Step 3 can not begin until the Step 2 circuit is complete and operational Don’t continue if Prof. Fontecchio has not checked your ADC circuit hardware
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ECE-L304 Lecture 3 7 This Week DC testing Observation of data bus
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This note was uploaded on 09/25/2011 for the course ECEL 304 taught by Professor Fontecchio during the Winter '07 term at Drexel.

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Lecture3 - ECE-L304 Lecture 3 Review of Step 2 Introduction...

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