Lecture6 - ECE-L304 Lecture 6 Review of Step 4 Introduction...

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ECE-L304 Lecture 6 Review of Step 4 Introduction to Step 5 Adding the on-board timer
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2 Step 4 Review Report writing in progress Due in 7-205 on your lab day
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3 Step 4 Review What did we learn? Stable address, stable data, write 590 counters have an error when CCK=RCK There is a propagation delay through 590 counter (how big?) Simple control (FlipFlop-based) is effective in controlling mode (RAM read/write)
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4 Step 4 Deliverables Part 1 Schematic, Simulation Plot A[15-0], W[7-0], RW1, RW0, R[7-0] vs time over span of 0 to 4 us Part 2 Schematic, Simulation Plot W[7-0], R[7-0], WE, RE, RCO, AIN, AOUT vs time over one complete read/write cycle Answer questions [Extra credit] Correct the timing flaw in the 590 count at the transition from write to read?
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5 Step by Step Step 1 Review of ADC and DAC Step 2 Build the ADC circuit Step 3 Build the DAC circuit Step 4 Introduce static RAM Step 5 Build the on-board clock Step 6 Introduce control logic Step 7 Final changes
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6 Project Circuit Progress to Date ADC DAC Control 8 8 RAM
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7 Project Circuit Step 5 Blocks ADC DAC 8 8 RAM Address Gen R/W Control Clock
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8 The 555 Timer A handy addition to the circuit designer’s “toolbox” capable of producing accurate time delays periods ranging from microseconds through hours. useful for astable oscillator operation maintains an accurately controlled free running frequency and duty cycle with only 2 external resistors and 1 capacitor.
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9 The 555 Timer Features Accurate Timing From Microseconds Through Hours Astable and Monostable Operation Adjustable Duty Cycle Output Capable of Sourcing or Sinking up to 200mA Output Capable of Driving TTL Devices Normally ON and OFF Outputs
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This note was uploaded on 09/25/2011 for the course ECEL 304 taught by Professor Fontecchio during the Winter '07 term at Drexel.

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Lecture6 - ECE-L304 Lecture 6 Review of Step 4 Introduction...

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