Step6 - ECEL 304 ECE Laboratory IV Winter 06-07 Dr....

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ECEL 304 ECE Laboratory IV Winter 06-07 Dr. Fontecchio Step 6 Introduce Control Logic Functionality Prelab Read the data sheets for the 74LS112 Dual JK Flip Flop, 74LS08 Quad AND gate, and 74LS590 8-bit counter. Complete the Step 6 Prelab Worksheet Build Address Generator Assemble a 16 bit address generator using two 74LS590 8-bit counters. To get full credit for your hardware, design a simple modification to create a 17th bit. The memory chip will require all 17 bits to get the full use of the 1 MB available and to maximize the record time. Use your 555 timer circuit as the clock. o Connect your address generator to the RAM address wire wrap pins in the lower center of your board. o Observe the address generator outputs on the logic analyzer and confirm functionality. Try to find the transition from decimal count 65536 to 0. Since our analyzer has only 16 bits, watch the highest 16 bits on a 17-bit counter. Save a screen capture of your analyzer result for your report. Add two AND gates in series between the clock input and the address
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This note was uploaded on 09/25/2011 for the course ECEL 304 taught by Professor Fontecchio during the Winter '07 term at Drexel.

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Step6 - ECEL 304 ECE Laboratory IV Winter 06-07 Dr....

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