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Assignment2 - ELEC 3500 Assignment 2 Due on 11th Feb Total...

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ELEC 3500: Assignment 2 Due on 11th Feb. Total marks: 25 1. Predict the final value of y for the following cases 2 Marks (a) reg [2:0] y; . . . y = 3’b101; (b) reg [2:0] y; . . . y = 4’b1101; (c) reg [3:1] y; . . . y = 4’b1101; (d) reg [2:0] y; . . . y = 10; 2. Write a module that implements y = A ( B + C ) using 2 Marks (a) Structural code (b) Behavioral code 3. Registers a, b are declared as reg [2:0] a,b; . a and b have initial values of 3 and 1 respectively. Find the values of a and b after each of the following Verilog codes are executed. 6 Marks (a) a = b + 2; b = a + 2; (b) b = a + 2; a = b + 2; (c) a <= b + 2; b <= a + 2; (d) b <= a + 2; a <= b + 2; (e) b = a && b; a = b & a; (f) a <= |b; b <= &a; 4. State whether the following Verilog procedures generate combinational logic, latches or flip-flops. If a procedure generates latches, modify the code to produce combinational logic. 5 Marks (a) wire A, B; reg Y; always @(A or B) begin Y = A|B; end (b) wire A, B, C; reg Y; always @(A or B) begin Y = (A|B)&C; end (c) reg s; reg q,r;
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always @(s) begin case (s) 1’b0: q = 1’b1; 1’b1: r = 1’b1; endcase end (d) reg [1:0] x; reg [1:0] q;
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