Assignment3 - 1 + X 2 + X 5 . 0.5 marks (b) Draw the state...

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ELEC 3500: Assignment 3 Due on 26th Feb at 10:00am in assignment dropbox. Total marks: 20 1. Draw the transistor level circuitry using CMOS logic for a functional D-latch constructed using a Mux. The Mux is implemented using pass transistors. 2 marks 2. (a) What is wrong with the following circuit? 1 mark (b) Suggest a cure. 1 mark 1D C1 1D C1 clk c d q1 q2 3. Draw the gate-level circuitry for a 2-bit binary down counter. 2 marks 4. Write the Verilog code to implement the following shift register. 2 marks 1D C1 1D C1 1D C1 clk d Q[2] Q[0] Q[1] 5. (a) A Mobius counter has 10 flip-flops. How many states will this counter have. 1 mark (b) The output of a Mobius counter running on a fast clock is interfaced with a synchronous circuit with a slower clock. Would there be a problem with this set-up. Justify your answer. 1 mark 6. (a) Draw the LFSR corresponding to the polynomial
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Unformatted text preview: 1 + X 2 + X 5 . 0.5 marks (b) Draw the state diagram for this LFSR indicating the value stored in the counter at each stage. 1 mark (c) Based on the state-diagram from (b) comment on whether 1 + X 2 + X 5 is a primitive or non-primitive polynomial. 0.5 marks 7. Design a counter that counts from 13 to 7. Draw the schematic. 2 marks 8. Write down the values that a 5 bit ripple counter would take during a transition from 15 to 16. 2 marks 9. Write the Verilog code to implement a 4-bit Gray code counter using look-up tables. 2 marks 10. Consider the following FSM. Let the present state be represented by CBA and the next-state be represented by c + b + a + . Find c + , b + and a + in terms of A , B , C and x by inspection. 2 marks x x x SA=001 SB=010 SC=100 x x...
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