Assignment4 - ELEC 3500 Assignment 4 Due on 1st April at...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ELEC 3500: Assignment 4 Due on 1st April at 10:00am in assignment dropbox. Total marks: 20 1. The fastest pulse in a given system that needs to be captured is observed to have a duration of 10ns. The setup time and hold time of the flip-flops in the design are given to be 1ns and 0ns respsctively. Calculate the minimum frequency of the clock in the design. 2 marks 2. The state diagram shown below describes a synchronous FSM with inputs x, y and z. z is a synchronous signal wheras x and y are asynchronous. Is there a problem with this design? If so, suggest a solution to the problem. 3 Marks z 001 010 111 000 z y y z x z x 110 100 S1 S2 S3 S4 S5 S6 z 3. Interface the gadget with the FSM shown in the following figure using debouncing. 3 Marks D1 D2 D3 D4 Gadget FSM Clock V1 V2 V3 V4 4. Find the maximum delay in the clock buffers for the shift registers shown. t clk = 10 ns (a) 2 Marks D C D C D C For all flip-flops Clock 2 Clock 3 Clock 1 t skew 1- 2 t skew 2- 3 D 1 D 2 D 3 Q 1 Q 2 Q 3 t P D = 1 ns t P D = 1 ns t CHQV = 2 ns t hold = 0 ns (b)...
View Full Document

{[ snackBarMessage ]}

Page1 / 2

Assignment4 - ELEC 3500 Assignment 4 Due on 1st April at...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online