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BB_Lecture32 Part 2 CMOSTransitionTimes_2_1

BB_Lecture32 Part 2 CMOSTransitionTimes_2_1 - EE 311...

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EE 311 Lecture 32 Part 2 Wedesday March 31, 2010 CMOS Inverter Transition Times Zubair Rehman
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2 t r & t f : rise & fall times for v I t THL : fall-time (High-To-Low) for v o t TLH : rise-time (Low-To-High) for v o t PHL : propagation delay time (High-To-Low) for v o t PLH : propagation delay time (Low-To-High) for v o
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3 C represents total capacitance load including internal capacitance, wiring, next stages, etc.
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4 V I Switch from Low-To-High V o Switches from High-To-Low Propagation Delay t PHL t = 0 - Capacitance Voltage = V DD t = 0 + Capacitance Voltage = V DD Q N (NMOS) Switches ON in Saturation i DN = 1 / 2 K n ’ (W n / L n ) (V DD - V tn ) 2 t PHL1 Point E Point F t = 0 + to t PHL1 | V o | = V DD - (V DD - V TN ) = V tn | Q| = C| V o | = |i DN | t = i DN t PHL1 t PHL1 = |C V o | / i DN = (C*V T ) / [ 1 / 2 K n ’ (W n / L n ) (V DD - V tn ) 2 ] Point F to M where V o = V DD / 2 t = t PHL1 to t PHL1 + t PHL2 = t PHL Q N (NMOS) in Triode Region i DN = K n ’ (W n / L n )[(V DD - V tn ) V o - 1 / 2 V o 2 ] Need Minus Sign - Must solve differential equation - C dV = i dt or dt = (- C * dV ) / i
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5 Consult Integral Tables
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