Lecture 35 Part 1 Synthesis of CMOS Logic Gates_1

# Lecture 35 Part 1 Synthesis of CMOS Logic Gates_1 -...

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EE 311 Lecture 35 Part 1 Wednesday April 7, 2010 10.3 Synthesis of CMOS Logic Gates Zubair Rehman

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2 1. The PDN can be most directly synthesized by expressing Y (Inverse of Y) as a function of uncomplemented variables. If complemented variables appear in this expression, additional inverters will be required to generate them. PUN is the dual of PDN 1. The PUN can be most directly synthesized by expressing Y as a function of the complemented variables and then applying the uncomplemented variables to the Gates of the PMOS transistors. If uncomplemented variables appear in the expression, additional inverters will be needed. PDN is the dual of PUN
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Unformatted text preview: Obtaining the PUN from the PDN and Vice Versa 1) PUN & PDN are duals of one another. 2) A series branch in one corresponds to a parallel branch in the other. 3) Inputs are the same in dual e.q. Input A in PDN is Input A in PUN (In other words do not replace A in PDN by A in PUN) Example: Y = A(B+CD) Y = A(B+CD) Synthesize PDN PUN is Dual of PDN Y = A+B(C+D) Y = A+B(C+D) 3 Figure 10.4 CMOS Realization Of A Complex Gate Y = A(B + CD) Synthesize PDN 1. A in series with (B + CD) 2. B in parallel with CD with C & D in series PUN is the Dual A is one // path BCD is 2 nd // path With B in series with CD which are in series...
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Lecture 35 Part 1 Synthesis of CMOS Logic Gates_1 -...

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