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Lecture 37 Part 1 Dynamic Logic Gates_1

Lecture 37 Part 1 Dynamic Logic Gates_1 - EE 311 Lecture 37...

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EE 311 Lecture 37 Part 1 Monday April 12, 2010 10.6 Dynamic Logic Circuits Precharge & Evaluation Leakage Current Problem Charge Sharing Problem Cascading Problem Exercises 10.10 & 10.11 Zubair Rehman
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2 Φ= Clock Signal ΦLow Q p On (Q e Off) C L charges to V DD This is Precharge phase ΦHigh Q p Off (Q e On) This is Evaluation phase Note that the PDN is the same as in a CMOS Logic Gate but that the PUN is much simpler and there is a considerable area reduction.
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3 Evaluation Phase (Q p OFF) PDN OFF No path for C L to discharge through Y remains High t PLH = 0 (does not exist) PDN ON Path for C L to discharge to GND C L discharges & Y decreases t PHL > 0 V IL = V tn & V IH = V tn NM L = V IL - V OL = V tn - 0 = V tn NM H = V OH - V IH = V DD - V tn
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4 Leakage Current Problem NMOS n + drain to p-substrate is reversed biased but there is a non-zero reverse bias current that slowly discharges C L . Clock frequency must be high enough so that C L is refreshed adequately.
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