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Unformatted text preview: EE 311 Lecture 37 Part 2 Monday April 12, 2010 & Lecture 38 Continuation on Exercise 10.10 (13.10) & Exercise 10.11 (13.11) Equivalent Transistor Model PSpice Simulations Problem 10.61 (13.61) Min. Clock Freq. Exercise 10.12 Cascading Problem Zubair Rehman 2 Consider a four-input NAND gate realized in dynamic logic form in a CMOS process technology for which μ n C ox = 50 μ A/V 2 , μ p C ox = 20 μ A/V 2 , V TN = |V TP | = 1 V & V DD = 5 V. In order to keep C L small, minimum-size NMOS devices are used for which (W/L) n = 4 μ m / 2 μ m (This includes Q e ). The PMOS precharge transistor has (W/L) = 6 μ m / 2 μ m. The total capacitance C L is 30 fF. 13.10 Consider the precharge operation with the gate of Q p falling to 0 V, and assume at t = 0, C L is fully discharged. We wish to calculate the rise time of the output voltage, defined as the time for V y to rise from 10 % to 90 % of the final value of 5 V. Find the current at V y = 0.5 V (10% of 5 V) and at V y = 4.5 V (90 % of 5 V), then compute an approximate value for t r , where t r = C L (4.5 - 0.5) / I av where I av is the average of the two currents. Answer: 480 μ A; 112 μ A; 0.4 ns 13.11 Next, consider the computation of the high-to-low propagation delay time t PHL . Find the equivalent W/L ratio of the five NMOS transistors in series. Then find the discharge current at V y = 5 V and at V y = 2.5 V. Finally use the average of these two currents to compute an...
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- Spring '09
- Transistor, Vdd, vy, Qp, Tphl, W/L