Lecture 38 Part 1 Problem10.62 &10.61_1

Lecture 38 Part 1 Problem10.62 &10.61_1 -...

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EE 311 Lecture 38 Wednesday April 14,2010 Problem 10.62(13.62) Zubair Rehman For the four-input dynamic-logic NAND gate analyzed in Exercises 10.10 and 10.11, estimate the maximum clocking frequency allowed.
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2 Exercise 13.10 t r = 0.4 ns rise-time during precharge Exercise 13.11 t PHL = 0.5 ns delay time during evaluation T φ > t r + t PHL = 0.9 ns f φ < 1 / T φ = 1 / 0.9 ns = 1.1 GHz T clock / 2 > [t r * (100 % / 80 %)] = 1.25 t r T clock / 2 > x (t PHL * 2) = T clock > max{2 * 1.25t r , 4 t PHL } = T clock > max{2.5 t r , 4 t PHL } = max{1 ns, 2 ns} T clock ≥ 2 ns f clock ≤ 1 / maxT clock = 1 / 2 ns = 0.5 GHz
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3 EE 311 Lecture 38 Wednesday April14, 2010 Problem 10.61(13.61) Minimum Clock Frequency The leakage current in a dynamic-logic gate causes the capacitor C L to discharge during the evaluation phase even if the PDN is not
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Unformatted text preview: conducting. The amount of discharge that is allowable, determines the minimum clock frequency. 4 At the start of evaluation phase: v y = V DD But V y decreases because of I leakage even if PDN is not conducting v y = Q CL / C L = I leak t / C L ( t) max = [C L ( V y ) max ] / I leak = (30 fF * 0.5 V) / 1 pA = 15 ms T = T precharge + T evaluation 0 + ( t) max = 15 ms min f = 1 / T = 1 / 15 ms = 67 Hz Often the clock is a square wave with equal pre-charge and evaluate times. Then T = T precharge + T evaluation 2 * ( t) max = 2 * 15 ms = 30 ms min f = 1 / T = 1 / 30 ms = 33 Hz...
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Lecture 38 Part 1 Problem10.62 &amp;amp;10.61_1 -...

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