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Lecture 38 Part 2 Exercise 10.12 &amp; Domino Dynamic Logic_1

Lecture 38 Part 2 Exercise 10.12 & Domino Dynamic Logic_1

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1 Exercise 10.12 Two single-input dynamic-logic gates connected in a cascade, With the input to MQ1 high, during the evaluation phase, CL2 will partially discharge and output at Y2 (across CL2) will fall lower than VDD, which can cause logic malfunction. Following the recipe given in Exercise 10.12 it was determined that the output at Y2 (across CL2) decrease to 3.6 V before MQ2 was cutoff. The PSpice simulation result indicates that output at Y2 (across CL2) decreases to 3.4 V in good agreement with the calculation.

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3 PSpice Probe Plot of Clock Output, inverter 1 output, and inverter 2 output. The clock output is V(MQ1:g) [green trace] The inverter 1 output is V(CL1:2) [red trace] The inverter 2 output is V(CL2:2) [blue trace] Note that the inverter 2 output should equal VDD = 5 V but has fallen to 3.3686 V. To eliminate the decrease in the inverter 2 output, add CMOS inverters (Domino Dynamic CMOS)

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Unformatted text preview: 4 5 Domino Dynamic CMOS: Add two CMOS Inverters 6 VCLOCK is the input X1 is the output of the first Domino CMOS Gate and input to the first CMOS inverter Y1 is the output of the first CMOS inverter and input to the second Domino CMOS Gate X2 is the output of the second Domino CMOS Gate and input to the second CMOS inverter Y2 is the output of the second CMOS inverter 7 As shown in the plot of waveforms: 1 Vclock go from high to low at time zero. 2 V(X1) goes from low to high 3 V(Y1) = V(QN2:g) goes from high to low 4 V(X2) goes from low to high 5 (Y2) = V(QN4:g) goes from high to low 1 Vclock go from low to high at time 2 ns. 2 V(X1) goes from high to low 3 V(Y1) = V(QN2:g) goes from low to high 4 V(X2) goes from high to low 5 (Y2) = V(QN4:g) goes from low to high Note that all outputs reach O V or 5 V and that the t PHL for Inverter #2 is approximately double that of Inverter #1...
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Lecture 38 Part 2 Exercise 10.12 & Domino Dynamic Logic_1

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