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Lecture 39 11.1 LatchesFlipFlops_1

# Lecture 39 11.1 LatchesFlipFlops_1 - EE 311 Lecture 3...

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EE 311 Lecture 3 Friday April 16, 2010 11.1 Latches & Flip-Flops Zubair Rehman

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2 Friday April 16, 2010 Lecture 39 Section 11.1 (13.7 in 4 th ed.) Latches and Flip-Flops Fig. 11.1 (13.38 in 4 th ed.) (a) Basic Latch & (b) Feedback Loop Open & (c) Operating Points Fig. 11.2 (13.39 in 4 th ed.) Set-Reset (SR) Flip-Flop Based Upon Two NOR Gates Fig. JJW.AA Two-Input CMOS NOR Gate Fig. JJW.BB SR Flip-Flop Based Two-Input CMOS NOR Gates Fig. 11.13 (13.40 in 4 th ed.) Clocked CMOS SR Flip-Flop Example 11.1 (13.5 in 4 th ed.) Minimum (W/L) 5 = (W/L) 6 For Switching When Input Pulse Amplitudes = V DD . Important: Note use of Sedra-Smith Equivalent Transistor Model (W/L)eq =(W/L)/N
3 Latch is a basic memory element. Cross-coupled Inverter Implementation Break feedback loop at Z and sketch VTC (Voltage Transfer Curve). VTC is that of Two Inverters in Series.

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4 Combined VTC - Open Loop Figure: Determining the operating point of the latch Connect Output Z to Input W; V W = V Z Draw Line V W = V Z Intersections of Line V W = V Z & VTC Determine Operating Points. Points A & C : Stable Point B : Unstable Suppose the operating point is Point B V W = V WB Let there be noise present V W V W = V WB +
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