Lecture 40 Part 1Exercise 11.1 Using SedraSmithEquivalentTransistorModel_1

# Lecture 40 Part 1Exercise 11.1 Using SedraSmithEquivalentTransistorModel_1

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EE 311 & EEO 311 Lecture 39 Exercise 11.1 Clocked SR Flip-Flop Repeat Example 10.1 to determine (W/L) 5 so that switching is achieved when inputs S and V clock are at V DD /2 Sedra-Smith Equivalent Transistor Model Zubair Rehman

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2 Exercise 11.1 Clocked SR Flip-Flop Determine Minimum (W/L) 5 DD /2 μ n Cox = 50 μ A/V 2 μ p Cox = 20 μ A/V 2 n = 4 μ m / 2 μ m p = 10 μ m / 2 μ m
3 μ n Cox(W/L) n = 100 μ A/V 2 μ p Cox(W/L) p = 100 μ A/V 2 V TN = |V TP | = 1 V V DD = 5 V Q1-Q2 & Q3-Q4 are matched CMOS Inverters. Switching Threshold is at V I = V DD / 2 for a matched Inverter

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4 For Q to be set at 1 (V Q pull down V Q’ to the switching threshold V TH = V DD /2. DD /2. Sedra-Smith Equivalent NMOS Method 56 . For (W/L) 6 = (W/L) 5 (W/L) eq = 1 / 2 (W/L) 5 or 1 / 2 (W/L) 6 Simplified Schematic Q2 is Conducting because V Q = 0 Whatever Capacitance C
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Unformatted text preview: L is at node Q’ is being charge thru Q2 and being discharged thru Q56 To discharge C L We Require i D56 ≥ i D2 V GSQ56 = V DD /2 V DD = V SD2 + V DS56 V Q’ = V DD /2 at Switching Threshold V SD2 = V DS56 = V DD /2 i DQ56 ≥ i DQ2 5 Solution Based Upon Equations Q2 V SG = V DD V SD = V DD /2 = 2.5 V V SG- |V TP | = 5 - 1 = 4 V > V SD = 2.5 V or V SD < V SG- |V TP | Triode Region For Q2 i DQ2 = μ p C ox (W/L) 2 [(V SG- |V TP |)V SD- 1 / 2 V SD 2 ] = 100 * [(4V) * 2.5 V - 1 / 2 * (2.5 V) 2 ] = 687.5 μ A Q56 V GS = V DD /2 = 2.5 V V DS = V DD /2 = 2.5 V V GS- V TN = 1.5 V < V DS = 2.5 V V DS > V GS- V TN Saturation i DQ56 = 1 / 2 μ n C ox (W/L) 56 [(V GS- V TN ) 2 ] = 1 / 2 * 50 * (W/L) 56 [1.5] 2 = 56.25 μ A * (W/L) 56 Setting i DQ56 ≥ i DQ2 56.25 μ A* (W/L) 56 ≥ 687.5 μ A (W/L) 56 ≥ (687.5) / (56.25) = 12.22 (W/L) 5 = (W/L) 6 ≥ 2 * (W/L) 56 = 2 * 12.22 = 24.44...
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Lecture 40 Part 1Exercise 11.1 Using SedraSmithEquivalentTransistorModel_1

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