Lecture 40 Part 2 Exercise 11.2 ClockedSRFlipFlop_1

# Lecture 40 Part 2 Exercise 11.2 ClockedSRFlipFlop_1 - EE...

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EE 311 & EEO 311 Lecture 39 Exercise 11.2 Clocked SR Flip-Flop Determine Minimum Width of Set Pulse Sedra-Smith Equivalent Transistor Model Zubair Rehman

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We wish to determine the minimum required width of the set pulse. Toward that end: (a) first consider the time for V Q’ in the circuit of the Figure to fall from V DD to V DD /2. Assume that the total capacitance between the Q’ node and ground is 50 fF. Determine t PHL by finding the average current available to discharge the capacitance over the voltage range V DD to V DD /2. Remember that Q 2 will be conducting a current that unfortunately reduces the current available to discharge C. Assume (W/L) 5 = (W/L) 6 = 8, and use the technology parameters given in Example 11.1. (b) Determine t PLH for V Q using the formula in Eq. (10.18). Assume a total node capacitance at Q of 50 fF. (c ) What is the minimum width required of the set pulse? Answer:
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Lecture 40 Part 2 Exercise 11.2 ClockedSRFlipFlop_1 - EE...

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