Lecture31 Part 2 Digital Logic Inverter_1

Lecture31 Part 2 Digital Logic Inverter_1 - EE 311 Lecture...

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CMOS Inverter Zubair Rehman EE 311 Lecture 31 Part 2 Monday March 29, 2010
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2 Review Digital Logic Inverter V IL = Max Value for V I Interpreted as 0 V IH = Min Value for V I Interpreted as 1
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3 Noise Margins 2nd Inverter Expects Logic Levels V OH OL Real Logic Systems are noisy. Suppose V I1 is high. Then V 01 is low. V I2 = V 01 + Noise < V IL V 02 is High Input Noise Margin for Low Input = NM L NM L = V IL - V OL Suppose V I1 is low. Then V 01 is high. V I2 = V 01 + Noise = V OH + Noise > V IH
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4 Structure of CMOS (Fig. 4.9 in 5 th ed. on p. 248) 1. Start with p-type body (Substrate) 2. Diffuse n-well for PMOS 3. 4. 5. Grow Gate Oxide Polysilicon is gate contact Thick SiO 2 provides isolation Not Shown - Contacts to p-type body & n-well
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5 NMOS Circuit Symbols ( Fig. 4.10 in 5 th ed. on p. 249)
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6 PMOS Circuit Symbol
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7 CMOS Inverter (Fig. 4.53 in 5 th ed. on p. 337) Figure 5.55 (b) Indicates p-type body connected sources of NMOS & n-type well connected source of PMOS
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Lecture31 Part 2 Digital Logic Inverter_1 - EE 311 Lecture...

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