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tutorial7 - CS 230 Tutorial 7 February 28, 2011 Jonathan...

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CS 230 Tutorial 7 February 28, 2011 Jonathan Rodriguez j2rodrig@uwaterloo.ca
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Tutorial 7 • Pipelines in the “Real World” • Cache and Memory Latencies • Q&A: Assignment & Other Questions
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Pipelines in the “Real World” Most popular CPU architecture: x86 – 8086/8088, 80286, 80386 – 80486 – Pentium (or 586) – Pentium II / Pentium Pro (or 686) – Pentium III, 4, and more …
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80386 • Introduced in 1985 • CISC (Complex Instruction Set Computer) • 3 stage pipeline – Instruction Fetch – Decode – Execute (includes writeback) • Fastest execution: 2 cycles per instruction • Memory accesses extra • Complex instructions extra
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80486 • Introduced in 1989 • RISC (Reduced Instruction Set Computer) • 5 stage pipeline – 2 decode stages to translate CISC into RISC • Fetch, Decode1, Decode2, Execute, Writeback – Conditional Branch Failed: 1 cycle – Conditional Branch Taken: 3 cycles (stall) • Fastest execution: 1 cycle per instruction
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Pentium • Introduced in 1993
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This note was uploaded on 09/28/2011 for the course CS 230 taught by Professor Bb during the Spring '11 term at Waterloo.

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tutorial7 - CS 230 Tutorial 7 February 28, 2011 Jonathan...

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