VLSI_Class_Project_SRAM_2010(1)

VLSI_Class_Project_SRAM_2010(1) - EEL 5322 VLSI Circuits...

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Instructor: Eisenstadt SRAM project (Due Wednesday December 8, 2010) Abstract: 6T-SRAM Cell Design The area of the SRAM Cell is critical in determining the overall area of a large SRAM core. In addition, it is also important to ensure read and write stability by proper transistor sizing. The layout of the SRAM along with its sizing also determines the speed and power dissipation of the SRAM core. You will need to build and characterize a SRAM 6T cell and evaluate the following performance parameters: .1) Hold, Read and Write cell stability (static noise margins) as described in class lectures. 2. Capacitance added to wordlines and bitlines per SRAM cell. Estimate the diffusion capacitance and the gate capacitance of the access transistors. .3) Cell area, defined as the smallest rectangle tha can be drawn around the cell. Technology TSMC 0.25um Deep Submicron Min. Channel Length 0.24um VDD 2.5V Temperature 27 O C Input Data/Clock signal slopes 100ps Clock Phases Non-overlapping (40%/60%) Delay measurement Between 50% points References: Chapter 12, Rabaey IEEE Journal of Solid-State Circuits, Vol. SC-19, No.-.5, Oct. 1984. IEEE Journal of Solid-State Circuits, Vol. SC-20, No.-.5, Oct. 1985.
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This note was uploaded on 10/02/2011 for the course ECE 5322 taught by Professor Ei during the Spring '10 term at University of Florida.

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VLSI_Class_Project_SRAM_2010(1) - EEL 5322 VLSI Circuits...

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