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hardware considerations (2) - COP 4600 Summer 2011...

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COP 4600: Intro To OS (Hardware Considerations) Page 1 © Dr. Mark Llewellyn COP 4600 – Summer 2011 Introduction To Operating Systems Hardware Considerations For OS Department of Electrical Engineering and Computer Science Computer Science Division University of Central Florida Instructor : Dr. Mark Llewellyn [email protected] HEC 236, 407-823-2790 http://www.cs.ucf.edu/courses/cop4600/sum2011
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COP 4600: Intro To OS (Hardware Considerations) Page 2 © Dr. Mark Llewellyn Top-Level Computer Components
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COP 4600: Intro To OS (Hardware Considerations) Page 3 © Dr. Mark Llewellyn Processor Registers User-visible registers Enable programmer to minimize main-memory references by optimizing register use Control and status registers Used by processor to control operating of the processor Used by privileged operating-system routines to control the execution of programs
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COP 4600: Intro To OS (Hardware Considerations) Page 4 © Dr. Mark Llewellyn User-Visible Registers May be referenced by machine language Available to all programs - application programs and system programs Types of registers Data Address Index Segment pointer Stack pointer
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COP 4600: Intro To OS (Hardware Considerations) Page 5 © Dr. Mark Llewellyn User-Visible Registers Address Registers Index Involves adding an index to a base value to get an address Segment pointer When memory is divided into segments, memory is referenced by a segment and an offset Stack pointer Points to top of stack
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COP 4600: Intro To OS (Hardware Considerations) Page 6 © Dr. Mark Llewellyn Control and Status Registers Program Counter (PC) Contains the address of an instruction to be fetched Instruction Register (IR) Contains the instruction most recently fetched Program Status Word (PSW) Condition codes Interrupt enable/disable Supervisor/user mode
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COP 4600: Intro To OS (Hardware Considerations) Page 7 © Dr. Mark Llewellyn Control and Status Registers Condition Codes or Flags Bits set by the processor hardware as a result of operations Examples Positive result Negative result Zero Overflow
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COP 4600: Intro To OS (Hardware Considerations) Page 8 © Dr. Mark Llewellyn Instruction Execution Two steps (Fetch/Decode & Execute) Processor reads instructions from memory Fetches into the MBR (MDR) Processor executes each instruction
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COP 4600: Intro To OS (Hardware Considerations) Page 9 © Dr. Mark Llewellyn Instruction Cycle
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COP 4600: Intro To OS (Hardware Considerations) Page 10 © Dr. Mark Llewellyn Instruction Fetch and Execute The processor fetches the instruction from memory Program counter (PC) holds address of the instruction to be fetched next Program counter is incremented after each fetch
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COP 4600: Intro To OS (Hardware Considerations) Page 11 © Dr. Mark Llewellyn Instruction Register Fetched instruction is placed in the instruction register Categories Processor-memory Transfer data between processor and memory Processor-I/O
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