5c - 31 base_counter counter1(clock,reset,1,temp); 32 33...

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exp_5c.v Tue Feb 22 14:58:47 2011 Page 1 1 `timescale 1ns / 1ps 2 ////////////////////////////////////////////////////////////////////////////////// 3 // Company: 4 // Engineer: 5 // 6 // Create Date: 14:14:32 02/22/2011 7 // Design Name: 8 // Module Name: exp_5c 9 // Project Name: 10 // Target Devices: 11 // Tool versions: 12 // Description: 13 // 14 // Dependencies: 15 // 16 // Revision: 17 // Revision 0.01 - File Created 18 // Additional Comments: 19 // 20 ////////////////////////////////////////////////////////////////////////////////// 21 module exp_5c(clock, reset,parity); 22 23 parameter n =42; 24 25 input clock; 26 input reset; 27 output parity; 28 29 wire [n-1:0]temp; 30
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Unformatted text preview: 31 base_counter counter1(clock,reset,1,temp); 32 33 assign parity =^temp; 34 35 36 37 endmodule 38 39 module base_counter(clock,reset, en, Q); 40 parameter n = 42; 41 input clock; 42 input en; 43 input reset; 44 output reg [n-1:0] Q; 45 46 47 48 // Usage of asynchronous resets may negatively impact FPGA resources 49 // and timing. In general faster and smaller FPGA designs will 50 // result from not using asynchronous resets. Please refer to 51 // the Synthesis and Simulation Design Guide for more information. 52 53 54 55 always @( posedge clock or posedge reset) 56 if (reset) 57 Q <= 0; 58 else if (en) 59 Q <= Q + 1; 60 61 endmodule...
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This note was uploaded on 10/02/2011 for the course EE 2720 taught by Professor Desouza during the Fall '08 term at LSU.

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