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document2 - parameter n =4; 24 25 input reset; 26 input en;...

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exp_5b.v Tue Feb 22 14:09:29 2011 Page 1 1 `timescale 1ns / 1ps 2 ////////////////////////////////////////////////////////////////////////////////// 3 // Company: 4 // Engineer: 5 // 6 // Create Date: 13:43:39 02/22/2011 7 // Design Name: 8 // Module Name: exp_5b 9 // Project Name: 10 // Target Devices: 11 // Tool versions: 12 // Description: 13 // 14 // Dependencies: 15 // 16 // Revision: 17 // Revision 0.01 - File Created 18 // Additional Comments: 19 // 20 ////////////////////////////////////////////////////////////////////////////////// 21 module exp_5b(reset, en, load, Q, D, clock); 22 23
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Unformatted text preview: parameter n =4; 24 25 input reset; 26 input en; 27 input load; 28 output reg [n-1:0] Q; 29 input [n-1:0] D; 30 input clock; 31 32 33 // Usage of asynchronous resets may negatively impact FPGA resources 34 // and timing. In general faster and smaller FPGA designs will 35 // result from not using asynchronous resets. Please refer to 36 // the Synthesis and Simulation Design Guide for more information. 37 38 39 40 always @( posedge clock or posedge reset) 41 if (reset) 42 Q <= 0; 43 else if (en) 44 if (load) 45 Q <= D; 46 else 47 Q <= Q + 1; 48 49 50 endmodule 51 52...
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